/*ibm/fxp.hRegisters and datastructures of the Intel 82557, 82558, 82559, 82550,and 82562 fast ethernet controllers.Created:	Nov 2004 by Philip Homburg <philip@f-mnx.phicoh.com>*/#define VERBOSE 	0	/* display output during intialization *//* Revisions in PCI_REV */#define FXP_REV_82557A		0x01#define FXP_REV_82557B		0x02#define FXP_REV_82557C		0x03#define FXP_REV_82558A		0x04#define FXP_REV_82558B		0x05#define FXP_REV_82559A		0x06#define FXP_REV_82559B		0x07#define FXP_REV_82559C		0x08#define FXP_REV_82559ERA	0x09#define FXP_REV_82550_1 	0x0C#define FXP_REV_82550_2		0x0D#define FXP_REV_82550_3		0x0E#define FXP_REV_82551_1		0x0F#define FXP_REV_82551_2		0x10/* Control/Status Registers (CSR). The first 8 bytes are called * System Control Block (SCB) */#define SCB_STATUS	0x00	/* Lower half of the SCB status word. CU and				 * RU status.				 */#define	    SS_CUS_MASK		0xC0	/* CU Status */#define		SS_CU_IDLE		0x00	/* Idle */#define		SS_CU_SUSP		0x40	/* Suspended */#define		SS_CU_LPQA		0x80	/* LPQ Active */#define		SS_CU_HQPA		0xC0	/* HQP Active */#define	    SS_RUS_MASK		0x3C	/* RU Status */#define		SS_RU_IDLE		0x00	/* Idle */#define		SS_RU_SUSP		0x04	/* Suspended */#define		SS_RU_NORES		0x08	/* No Resources */#define		SS_RU_READY		0x10	/* Ready */						/* Other values are reserved */#define	    SS_RESERVED		0x03	/* Reserved */#define SCB_INT_STAT	0x01	/* Upper half of the SCB status word.				 * Interrupt status. Also used to acknoledge				 * interrupts.				 */#define		SIS_CX	0x80	/* CU command with interrupt bit set. On				 * 82557 also TNO Interrupt.				 */#define		SIS_FR	0x40	/* Frame Received */#define		SIS_CNA	0x20	/* CU Not Active */#define		SIS_RNR	0x10	/* RU Not Ready */#define		SIS_MDI	0x08	/* MDI read/write cycle completed */#define		SIS_SWI	0x04	/* Software Interrupt */#define		SIS_RES	0x02	/* Reserved */#define		SIS_FCP	0x01	/* Flow Control Pause Interrupt (82558 and				 * later, reserved on 82557)				 */#define SCB_CMD		0x02	/* Lower half of the SCB command word. CU and				 * RU commands.				 */#define	    SC_CUC_MASK		0xF0#define		SC_CU_NOP		0x00	/* NOP */#define		SC_CU_START		0x10	/* Start CU */#define		SC_CU_RESUME		0x20	/* Resume CU */#define		SC_CU_LOAD_DCA		0x40	/* Load Dump Counters Address */#define		SC_CU_DUMP_SC		0x50	/* Dump Statistical Counters */#define		SC_CU_LOAD_BASE		0x60	/* Load CU Base */#define		SC_CU_DUMP_RSET_SC	0x70	/* Dump and Reset Counters */#define		SC_CU_STATIC_RESUME	0xA0	/* Static Resume, 82558 and						 * above						 */#define	    SC_RESERVED		0x08	/* Reserved */#define	    SC_RUC_MASK		0x07	/* RU Command Mask */#define		SC_RU_NOP		0x00	/* NOP */#define		SC_RU_START		0x01	/* Start RU */#define		SC_RU_RESUME		0x02	/* Resume RU */#define		SC_RU_DMA_REDIR		0x03	/* DMA Redirect */#define		SC_RU_ABORT		0x04	/* Abort RU */#define		SC_RU_LOAD_HDR		0x05	/* Load Header Data Size */#define		SC_RU_LOAD_BASE		0x06	/* Load RU Base */#define SCB_INT_MASK	0x03	/* Upper half of the SCB command word. 				 * Interrupt mask. Can also be used to				 * generate a 'software' interrupt.				 */				/* The following 6 mask bits are not valid on				 * the 82557.				 */#define	    SIM_CX	0x80	/* Mask CX */#define	    SIM_FR	0x40	/* Mask FR */#define	    SIM_CNA	0x20	/* Mask CNA */#define	    SIM_RNR	0x10	/* Mask RNR */#define	    SIM_ER	0x08	/* Mask ER */#define	    SIM_FCP	0x04	/* Mask FCP */#define	    SIM_SI	0x02	/* Generate Software Interrupt */#define	    SIM_M	0x01	/* Mask all interrupts */#define SCB_POINTER	0x04	/* A 32-bit (pointer) argument for CU and RU				 * commands.				 */#define CSR_PORT	0x08	/* Control functions that bypass the SCB */#define	    CP_PTR_MASK		0xFFFFFFF0	/* Argument pointer */#define	    CP_CMD_MASK		0x0000000F	/* Commands bits */#define		CP_CMD_SOFT_RESET	0x00000000	/* Software reset */#define	    	    CSR_PORT_RESET_DELAY	10	/* Wait for reset to							 * complete. In micro							 * seconds.							 */#define		CP_CMD_SELF_TEST	0x00000001	/* Self test */#define		CP_CMD_SEL_RESET	0x00000002	/* Selective reset */#define		CP_CMD_DUMP		0x00000003	/* Dump */#define		CP_CMD_DUMP_WAKEUP	0x00000007	/* Dump and wake-up,							 * 82559 and later.							 */#define	CSR_RESERVED	0x0C	/* reserved, 16-bits */#define CSR_EEPROM	0x0E	/* EEPROM Control Register */#define	    CE_RESERVED	0xF0	/* Reserved */#define	    CE_EEDO	0x08	/* Serial Data Out  (of the EEPROM) */#define	    CE_EEDI	0x04	/* Serial Data In (to the EEPROM) */#define	    CE_EECS	0x02	/* Chip Select */#define	    CE_EESK	0x01	/* Serial Clock */#define CSR_RESERVED1	0x0F	/* Reserved */#define CSR_MDI_CTL	0x10	/* MDI Control Register, 32-bits */#define	    CM_RESERVED		0xC0000000	/* Reserved */#define	    CM_IE		0x20000000	/* Enable Interrupt */#define	    CM_READY		0x10000000	/* Command completed */#define	    CM_OPCODE_MASK	0x0C000000	/* Opcode */#define		CM_WRITE		0x04000000	/* Write */#define		CM_READ			0x08000000	/* Read */#define	    CM_PHYADDR_MASK	0x03E00000	/* Which PHY */#define		CM_PHYADDR_SHIFT 21#define	    CM_REG_MASK		0x001F0000	/* Which register in the PHY */#define	    	CM_REG_SHIFT	16#define	    CM_DATA_MASK	0x0000FFFF	/* Data to be read or written *//* Control Block List (CBL) commands */#define CBL_NOP		0	/* No-operation */#define CBL_AIS		1	/* Individual Address Setup */#define CBL_CONF	2	/* Configure NIC */#define CBL_MAS		3	/* Multicast Address Setup */#define CBL_XMIT	4	/* Transmit */#define CBL_LM		5	/* Load Microcode */#define CBL_DUMP	6	/* Dump Internal Registers */#define CBL_DIAG	7	/* Diagnose Command *//* Common command fields */#define CBL_C_CMD_MASK	0x0007	/* Command bits */#define CBL_C_EL	0x8000	/* End of CBL */#define CBL_C_S		0x4000	/* Suspend after the completion of the CB */#define CBL_C_I		0x2000	/* Request CX Interrupt */#define CBL_C_RES	0x1FF8	/* Reserved *//* Command flags */#define CBL_F_C		0x8000	/* Command has completed */#define CBL_F_RES1	0x4000	/* Reserved */#define CBL_F_OK	0x2000	/* Command was executed without errors */#define CBL_F_RES0	0x1FFF	/* Reserved *//* Individual Address Setup (1) */struct ias{	u16_t ias_status;	u16_t ias_command;	u32_t ias_linkaddr;	u8_t ias_ethaddr[6];	u8_t ias_reserved[2];};/* Configure (2) */#define CC_BYTES_NR	22	/* Number of configuration bytes */struct cbl_conf{	u16_t cc_status;	u16_t cc_command;	u32_t cc_linkaddr;	u8_t cc_bytes[CC_BYTES_NR];};/* Byte 0 */#define CCB0_RES	0xC0	/* Reserved (0) */#define CCB0_BYTECOUNT	0x3F	/* Byte Count (typically either 8 or 22) *//* Byte 1 */#define CCB1_RES	0x80	/* Reserved (0) */#define CCB1_TXFIFO_LIM	0x70	/* Transmit FIFO Limit, in DWORDS */#define		CTL_DEFAULT	0x00	/* 0 bytes */#define CCB1_RXFIFO_LIM	0x0F	/* Receive FIFO Limit */#define		CRL_DEFAULT	0x08	/* 32 bytes on 82557, 64 bytes on					 * 82558/82559.					 *//* Byte 2 */#define CCB2_AIFS	0xFF	/* Adaptive IFS */#define		CAI_DEFAULT	0/* Byte 3 */				/* Reserved (must be 0) on 82557 */#define CCB3_RES	0xF0	/* Reserved (0) */#define	CCB3_TWCL	0x08	/* Terminate Write on Cache Line */#define	CCB3_RAE	0x04	/* Read Alignment Enable */#define	CCB3_TE		0x02	/* Type Enable??? */#define	CCB3_MWIE	0x01	/* Memory Write and Invalidate (MWI) Enable				 * Additionally the MWI bit in the PCI				 * command register has to be set.				 * Recommended by Intel.				 *//* Byte 4 */#define CCB4_RES	0x80	/* Reserved (0) */#define CCB4_RXDMA_MAX	0x7F	/* Receive DMA Maximum Byte Count *//* Byte 5 */#define CCB5_DMBCE	0x80	/* DMA Maximum Byte Count Enable */#define CCB5_TXDMA_MAX	0x7F	/* Transmit DMA Maximum Byte Count *//* Byte 6 */#define CCB6_SBF	0x80	/* Save Bad Frames */#define CCB6_DORF	0x40	/* (Do not) Discard Overrun Receive Frame,				 * Set this bit to keep them.				 */#define CCB6_ESC	0x20	/* Extended Statistical Counter. Reserved				 * on 82557, must be set to 1.				 * Clear this bit to get more counters.				 */#define CCB6_ETCB	0x10	/* Extended Transmit CB. Reserved on 82557,				 * must be set to 1.				 * Clear this bit to use Extended TxCBs.				 */#define CCB6_CI_INT	0x08	/* CPU Idle (CI) Interrupt. Generate a				 * CI Int (bit set) or a CNA Int (bit clear)				 * when the CU goes to the idle state (or				 * to suspended for CNA).				 */#define CCB6_TNO_INT	0x04	/* Enable TNO Interrupt (82557 only) */#define CCB6_TCOSC	0x04	/* TCO Statistical Counter (82559 only) */#define CCB6_RES	0x02	/* Reserved, must be set to 1. Called "disable				 * direct rcv dma mode" by the FreeBSD				 * driver.				 */#define CCB6_LSCB	0x01	/* Late SCB Update. Only on 82557. *//* Byte 7 */#define CCB7_DTBD	0x80	/* Dynamic TBD. Reserved on 82557, should be				 * be set to 0.				 */#define CCB7_2FFIFO	0x40	/* (At Most) Two Frames in FIFO. Reserved on				 * 82557, should be set to 0.				 */#define CCB7_RES	0x38	/* Reserved (0) */#define CCB7_UR		0x06	/* Underrun Retry */#define	    CUR_0		0x00	/* No re-transmission */#define	    CUR_1		0x02	/* One re-transmission */#define	    CUR_2		0x04	/* Two re-transmissions, 1st retry with					 * 512 bytes.					 */#define	    CUR_3		0x06	/* Tree re-transmissions, 1st retry					 * with 512 bytes, 2nd retry with 1024.					 */#define CCB7_DSRF	0x01	/* Discard Short Receive Frames. *//* Byte 8 */#define CCB8_CSMAD	0x80	/* CSMA Disable. Reserved on 82557, should be				 * set to zero.				 */#define CCB8_RES	0x7E	/* Reserved (0) */#define CCB8_503_MII	0x01	/* 503 mode or MII mode. Reserved on 82558				 * and 82559, should be set to 1.				 *//* Byte 9 */#define CCB9_MMWE	0x80	/* Multicast Match Wake Enable. 82558 B-step				 * only, should be set to zero on other				 * devices.				 */#define CCB9_AWE	0x40	/* ARP Wake-up Enable. 82558 B-step only,				 * should be set to zero on other devices.				 */#define CCB9_LSCWE	0x20	/* Link Status Change Wake Enable. Available				 * on 82558 B-step and 82559. Should be				 * set to zero on 82557 and 82558 A-step				 */#define CCB9_VARP	0x10	/* VLAN ARP (82558 B-step) or VLAN TCO (82559).				 * Should be zero on 82557 and 82558 A-step				 */#define CCB9_RES	0x0E	/* Reserved (0) */#define CCB9_TUC	0x01	/* TCP/UDP Checksum. 82559 only, should be				 * zero on other devices.