library verilog;use verilog.vl_types.all;entity beh_sram is    generic(        M_DLY           : integer := 9    );    port(        clk             : in     vl_logic;        dat             : inout  vl_logic_vector(31 downto 0);        addr            : in     vl_logic_vector(9 downto 0);        \rd_\           : in     vl_logic;        \wr_\           : in     vl_logic    );end beh_sram;