Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Wed Apr 30 06:55:50 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off a2d -c a2d
Info: Selected device EPM1270T144C5 for design "a2d"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM570T144C5 is compatible
    Info: Device EPM570T144I5 is compatible
    Info: Device EPM1270T144I5 is compatible
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 18
Info: Automatically promoted some destinations of signal "sw0" to use Global clock
    Info: Destination "t_sck" may be non-global or may not use global clock
    Info: Destination "t_dacs" may be non-global or may not use global clock
    Info: Destination "t_dasck~477" may be non-global or may not use global clock
    Info: Destination "ram_part_addr[3]" may be non-global or may not use global clock
    Info: Destination "t_int[0]~408" may be non-global or may not use global clock
    Info: Destination "count2[5]~1029" may be non-global or may not use global clock
    Info: Destination "count3[0]~2092" may be non-global or may not use global clock
    Info: Destination "comb~21" may be non-global or may not use global clock
    Info: Destination "ram_part_addr[2]~4857" may be non-global or may not use global clock
    Info: Destination "comb~3774" may be non-global or may not use global clock
    Info: Limited to 10 non-global destinations
Info: Pin "sw0" drives global clock, but is not placed in a dedicated clock pin position
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 16.376 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X9_Y5; Fanout = 8; REG Node = 'count1[1]'
    Info: 2: + IC(0.696 ns) + CELL(0.740 ns) = 1.436 ns; Loc. = LAB_X9_Y5; Fanout = 3; COMB Node = 'Equal0~84'
    Info: 3: + IC(1.059 ns) + CELL(0.200 ns) = 2.695 ns; Loc. = LAB_X9_Y5; Fanout = 3; COMB Node = 'LessThan12~244'
    Info: 4: + IC(1.562 ns) + CELL(0.740 ns) = 4.997 ns; Loc. = LAB_X9_Y6; Fanout = 3; COMB Node = 'LessThan7~341'
    Info: 5: + IC(0.983 ns) + CELL(0.200 ns) = 6.180 ns; Loc. = LAB_X9_Y6; Fanout = 7; COMB Node = 'LessThan7~342'
    Info: 6: + IC(0.269 ns) + CELL(0.914 ns) = 7.363 ns; Loc. = LAB_X9_Y6; Fanout = 3; COMB Node = 'count3[1]~2089'
    Info: 7: + IC(1.591 ns) + CELL(0.740 ns) = 9.694 ns; Loc. = LAB_X10_Y8; Fanout = 1; COMB Node = 'ram_part_addr[2]~4851'
    Info: 8: + IC(2.131 ns) + CELL(0.200 ns) = 12.025 ns; Loc. = LAB_X11_Y6; Fanout = 1; COMB Node = 'ram_part_addr[2]~4852'
    Info: 9: + IC(0.443 ns) + CELL(0.740 ns) = 13.208 ns; Loc. = LAB_X11_Y6; Fanout = 3; COMB Node = 'ram_part_addr[2]~4857'
    Info: 10: + IC(1.925 ns) + CELL(1.243 ns) = 16.376 ns; Loc. = LAB_X10_Y7; Fanout = 26; REG Node = 'ram_part_addr[0]'
    Info: Total cell delay = 5.717 ns ( 34.91 % )
    Info: Total interconnect delay = 10.659 ns ( 65.09 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 13% of the available device resources. Peak interconnect usage is 14%
    Info: The peak interconnect region extends from location X0_Y0 to location X8_Y11
Info: Fitter routing operations ending: elapsed time is 00:00:02
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 1 warning
    Info: Allocated 150 megabytes of memory during processing
    Info: Processing ended: Wed Apr 30 06:55:55 2008
    Info: Elapsed time: 00:00:05