{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Info: Started processing fast register assignments" {  } {  } 0 0 "Started processing fast register assignments" 0 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Info: Finished processing fast register assignments" {  } {  } 0 0 "Finished processing fast register assignments" 0 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Extra Info: Finished moving registers into LUTs: elapsed time is 00:00:00" {  } {  } 1 0 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "16.376 ns register register " "Info: Estimated most critical path is register to register delay of 16.376 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count1\[1\] 1 REG LAB_X9_Y5 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X9_Y5; Fanout = 8; REG Node = 'count1\[1\]'" {  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { count1[1] } "NODE_NAME" } } { "a2d.vhd" "" { Text "F:/電子設計/ram_da/a2d.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.696 ns) + CELL(0.740 ns) 1.436 ns Equal0~84 2 COMB LAB_X9_Y5 3 " "Info: 2: + IC(0.696 ns) + CELL(0.740 ns) = 1.436 ns; Loc. = LAB_X9_Y5; Fanout = 3; COMB Node = 'Equal0~84'" {  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.436 ns" { count1[1] Equal0~84 } "NODE_NAME" } } { "a2d.vhd" "" { Text "F:/電子設計/ram_da/a2d.vhd" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.059 ns) + CELL(0.200 ns) 2.695 ns LessThan12~244 3 COMB LAB_X9_Y5 3 " "Info: 3: + IC(1.059 ns) + CELL(0.200 ns) = 2.695 ns; Loc. = LAB_X9_Y5; Fanout = 3; COMB Node = 'LessThan12~244'" {  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.259 ns" { Equal0~84 LessThan12~244 } "NODE_NAME" } } { "a2d.vhd" "" { Text "F:/電子設計/ram_da/a2d.vhd" 147 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.562 ns) + CELL(0.740 ns) 4.997 ns LessThan7~341 4 COMB LAB_X9_Y6 3 " "Info: 4: + IC(1.562 ns) + CELL(0.740 ns) = 4.997 ns; Loc. = LAB_X9_Y6; Fanout = 3; COMB Node = 'LessThan7~341'" {  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.302 ns" { LessThan12~244 LessThan7~341 } "NODE_NAME" } } { "a2d.vhd" "" { Text "F:/電子設計/ram_da/a2d.vhd" 130 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.983 ns) + CELL(0.200 ns) 6.180 ns LessThan7~342 5 COMB LAB_X9_Y6 7 " "Info: 5: + IC(0.983 ns) + CELL(0.200 ns) = 6.180 ns; Loc. = LAB_X9_Y6; Fanout = 7; COMB Node = 'LessThan7~342'" {  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.183 ns" { LessThan7~341 LessThan7~342 } "NODE_NAME" } } { "a2d.vhd" "" { Text "F:/電子設計/ram_da/a2d.vhd" 130 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.269 ns) + CELL(0.914 ns) 7.363 ns count3\[1\]~2089 6 COMB LAB_X9_Y6 3 " "Info: 6: + IC(0.269 ns) + CELL(0.914 ns) = 7.363 ns; Loc. = LAB_X9_Y6; Fanout = 3; COMB Node = 'count3\[1\]~2089'" {  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.183 ns" { LessThan7~342 count3[1]~2089 } "NODE_NAME" } } { "a2d.vhd" "" { Text "F:/電子設計/ram_da/a2d.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.591 ns) + CELL(0.740 ns) 9.694 ns ram_part_addr\[2\]~4851 7 COMB LAB_X10_Y8 1 " "Info: 7: + IC(1.591 ns) + CELL(0.740 ns) = 9.694 ns; Loc. = LAB_X10_Y8; Fanout = 1; COMB Node = 'ram_part_addr\[2\]~4851'" {  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.331 ns" { count3[1]~2089 ram_part_addr[2]~4851 } "NODE_NAME" } } { "a2d.vhd" "" { Text "F:/電子設計/ram_da/a2d.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.131 ns) + CELL(0.200 ns) 12.025 ns ram_part_addr\[2\]~4852 8 COMB LAB_X11_Y6 1 " "Info: 8: + IC(2.131 ns) + CELL(0.200 ns) = 12.025 ns; Loc. = LAB_X11_Y6; Fanout = 1; COMB Node = 'ram_part_addr\[2\]~4852'" {  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.331 ns" { ram_part_addr[2]~4851 ram_part_addr[2]~4852 } "NODE_NAME" } } { "a2d.vhd" "" { Text "F:/電子設計/ram_da/a2d.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.443 ns) + CELL(0.740 ns) 13.208 ns ram_part_addr\[2\]~4857 9 COMB LAB_X11_Y6 3 " "Info: 9: + IC(0.443 ns) + CELL(0.740 ns) = 13.208 ns; Loc. = LAB_X11_Y6; Fanout = 3; COMB Node = 'ram_part_addr\[2\]~4857'" {  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.183 ns" { ram_part_addr[2]~4852 ram_part_addr[2]~4857 } "NODE_NAME" } } { "a2d.vhd" "" { Text "F:/電子設計/ram_da/a2d.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.925 ns) + CELL(1.243 ns) 16.376 ns ram_part_addr\[0\] 10 REG LAB_X10_Y7 26 " "Info: 10: + IC(1.925 ns) + CELL(1.243 ns) = 16.376 ns; Loc. = LAB_X10_Y7; Fanout = 26; REG Node = 'ram_part_addr\[0\]'" {  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.168 ns" { ram_part_addr[2]~4857 ram_part_addr[0] } "NODE_NAME" } } { "a2d.vhd" "" { Text "F:/電子設計/ram_da/a2d.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.717 ns ( 34.91 % ) " "Info: Total cell delay = 5.717 ns ( 34.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.659 ns ( 65.09 % ) " "Info: Total interconnect delay = 10.659 ns ( 65.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "16.376 ns" { count1[1] Equal0~84 LessThan12~244 LessThan7~341 LessThan7~342 count3[1]~2089 ram_part_addr[2]~4851 ram_part_addr[2]~4852 ram_part_addr[2]~4857 ram_part_addr[0] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "13 14 " "Info: Average interconnect usage is 13% of the available device resources. Peak interconnect usage is 14%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X0_Y0 X8_Y11 " "Info: The peak interconnect region extends from location X0_Y0 to location X8_Y11" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Info: Fitter routing operations ending: elapsed time is 00:00:02" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "150 " "Info: Allocated 150 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 30 06:55:55 2008 " "Info: Processing ended: Wed Apr 30 06:55:55 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/電子設計/ram_da/a2d.fit.smsg " "Info: Generated suppressed messages file F:/電子設計/ram_da/a2d.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}