{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 30 06:55:38 2008 " "Info: Processing started: Wed Apr 30 06:55:38 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off a2d -c a2d " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off a2d -c a2d" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "a2d.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file a2d.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 a2d-aa " "Info: Found design unit 1: a2d-aa" {  } { { "a2d.vhd" "" { Text "F:/電子設(shè)計(jì)/ram_da/a2d.vhd" 27 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 a2d " "Info: Found entity 1: a2d" {  } { { "a2d.vhd" "" { Text "F:/電子設(shè)計(jì)/ram_da/a2d.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "a2d " "Info: Elaborating entity \"a2d\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR_HDR" "" "Warning: Converted TRI buffer or tri-state bus to logic, or removed OPNDRN" { { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "t_ramdata\[0\]~24 " "Warning: Converting TRI node \"t_ramdata\[0\]~24\" that feeds logic to a wire" {  } { { "a2d.vhd" "" { Text "F:/電子設(shè)計(jì)/ram_da/a2d.vhd" 48 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "t_ramdata\[1\]~25 " "Warning: Converting TRI node \"t_ramdata\[1\]~25\" that feeds logic to a wire" {  } { { "a2d.vhd" "" { Text "F:/電子設(shè)計(jì)/ram_da/a2d.vhd" 48 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "t_ramdata\[2\]~26 " "Warning: Converting TRI node \"t_ramdata\[2\]~26\" that feeds logic to a wire" {  } { { "a2d.vhd" "" { Text "F:/電子設(shè)計(jì)/ram_da/a2d.vhd" 48 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "t_ramdata\[3\]~27 " "Warning: Converting TRI node \"t_ramdata\[3\]~27\" that feeds logic to a wire" {  } { { "a2d.vhd" "" { Text "F:/電子設(shè)計(jì)/ram_da/a2d.vhd" 48 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "t_ramdata\[4\]~28 " "Warning: Converting TRI node \"t_ramdata\[4\]~28\" that feeds logic to a wire" {  } { { "a2d.vhd" "" { Text "F:/電子設(shè)計(jì)/ram_da/a2d.vhd" 48 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "t_ramdata\[5\]~29 " "Warning: Converting TRI node \"t_ramdata\[5\]~29\" that feeds logic to a wire" {  } { { "a2d.vhd" "" { Text "F:/電子設(shè)計(jì)/ram_da/a2d.vhd" 48 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "t_ramdata\[6\]~30 " "Warning: Converting TRI node \"t_ramdata\[6\]~30\" that feeds logic to a wire" {  } { { "a2d.vhd" "" { Text "F:/電子設(shè)計(jì)/ram_da/a2d.vhd" 48 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "t_ramdata\[7\]~31 " "Warning: Converting TRI node \"t_ramdata\[7\]~31\" that feeds logic to a wire" {  } { { "a2d.vhd" "" { Text "F:/電子設(shè)計(jì)/ram_da/a2d.vhd" 48 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0}  } {  } 0 0 "Converted TRI buffer or tri-state bus to logic, or removed OPNDRN" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "t_dadata\[3\] t_dadata\[0\] " "Info: Duplicate register \"t_dadata\[3\]\" merged to single register \"t_dadata\[0\]\"" {  } { { "a2d.vhd" "" { Text "F:/電子設(shè)計(jì)/ram_da/a2d.vhd" 48 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "t_dadata\[2\] t_dadata\[0\] " "Info: Duplicate register \"t_dadata\[2\]\" merged to single register \"t_dadata\[0\]\"" {  } { { "a2d.vhd" "" { Text "F:/電子設(shè)計(jì)/ram_da/a2d.vhd" 48 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "t_dadata\[13\] t_dadata\[0\] " "Info: Duplicate register \"t_dadata\[13\]\" merged to single register \"t_dadata\[0\]\"" {  } { { "a2d.vhd" "" { Text "F:/電子設(shè)計(jì)/ram_da/a2d.vhd" 48 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "t_dadata\[12\] t_dadata\[1\] " "Info: Duplicate register \"t_dadata\[12\]\" merged to single register \"t_dadata\[1\]\"" {  } { { "a2d.vhd" "" { Text "F:/電子設(shè)計(jì)/ram_da/a2d.vhd" 48 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "t_dadata\[14\] t_dadata\[1\] " "Info: Duplicate register \"t_dadata\[14\]\" merged to single register \"t_dadata\[1\]\"" {  } { { "a2d.vhd" "" { Text "F:/電子設(shè)計(jì)/ram_da/a2d.vhd" 48 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "t_dadata\[0\] data_in GND " "Warning: Reduced register \"t_dadata\[0\]\" with stuck data_in port to stuck value GND" {  } { { "a2d.vhd" "" { Text "F:/電子設(shè)計(jì)/ram_da/a2d.vhd" 48 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "a2d.vhd" "" { Text "F:/電子設(shè)計(jì)/ram_da/a2d.vhd" 48 -1 0 } } { "a2d.vhd" "" { Text "F:/電子設(shè)計(jì)/ram_da/a2d.vhd" 48 -1 0 } } { "a2d.vhd" "" { Text "F:/電子設(shè)計(jì)/ram_da/a2d.vhd" 48 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "8 8 " "Info: 8 registers lost all their fanouts during netlist optimizations. The first 8 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "t_ramdata\[0\]~en " "Info: Register \"t_ramdata\[0\]~en\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "t_ramdata\[1\]~en " "Info: Register \"t_ramdata\[1\]~en\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "t_ramdata\[2\]~en " "Info: Register \"t_ramdata\[2\]~en\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "t_ramdata\[3\]~en " "Info: Register \"t_ramdata\[3\]~en\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "t_ramdata\[4\]~en " "Info: Register \"t_ramdata\[4\]~en\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "t_ramdata\[5\]~en " "Info: Register \"t_ramdata\[5\]~en\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "t_ramdata\[6\]~en " "Info: Register \"t_ramdata\[6\]~en\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "t_ramdata\[7\]~en " "Info: Register \"t_ramdata\[7\]~en\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "416 " "Info: Implemented 416 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "12 " "Info: Implemented 12 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "388 " "Info: Implemented 388 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 10 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "140 " "Info: Allocated 140 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 30 06:55:49 2008 " "Info: Processing ended: Wed Apr 30 06:55:49 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}