-- tlc0820ac ---a/d轉換
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; 
use ieee.std_logic_unsigned.all;
entity a2d is
port(clk :in std_logic;--輸入時鐘信號50MHz
	 rst : in std_logic;  --復位
	
--	 mode :out std_logic;  --0820模式，1為寫0為讀，懸空相當于低
	 cs : out std_logic;
	 rd : out std_logic;
	 int : in std_logic;
	 datain : in std_logic_vector(7 downto 0)
--	 dataout : out std_logic_vector(7 downto 0)
	);
end a2d;
architecture aa of a2d is
signal t_rd, t_cs : std_logic;
signal count: integer range 0 to 154; --total采樣間隔為50+2600=3100ns
signal t_int: integer range 0 to 15;		--350ns 肯定夠int變為高了
signal t_data :std_logic_vector(7 downto 0);

begin
process(clk,int,rst)
begin

--異步復位
if rst='1' then
	count <= 0;
	t_cs <= '1';
	t_rd <= '1';
	t_data <= "00000000";

--計數器
	elsif(clk'event and clk='1') then
		if count=154 then
			count<=0;
		else 
			count<=count+1;
		end if;

		--時序控制
		if count < 3 then
			t_cs<='1';
			t_rd<='1';
		elsif count < 23 then
			t_cs<='0';
			t_rd<='1';
		else
			t_cs<='0';
			t_rd<='0';
			if int='0' then
				t_int<=t_int+1;
			else
				t_int<=0;
			end if;
			if t_int = 2 then
				t_data <= datain;
			end if;
		end if;
end if;
end process;
cs<=t_cs;
rd<=t_rd;
--dataout<=t_data;
--dclk <= count;

end aa;