;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 29    ;
;     -- asynchronous clear/load mode         ; 50    ;
;                                             ;       ;
; Total registers                             ; 101   ;
; Total logic cells in carry chains           ; 48    ;
; I/O pins                                    ; 28    ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 101   ;
; Total fan-out                               ; 1559  ;
; Average fan-out                             ; 3.75  ;
+---------------------------------------------+-------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                   ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |a2d                       ; 388 (388)   ; 101          ; 0          ; 28   ; 0            ; 287 (287)    ; 20 (20)           ; 81 (81)          ; 48 (48)         ; 0 (0)      ; |a2d                ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                              ;
+----------------------------------------+----------------------------------------+
; Register name                          ; Reason for Removal                     ;
+----------------------------------------+----------------------------------------+
; t_ramdata[0]~en                        ; Lost fanout                            ;
; t_ramdata[1]~en                        ; Lost fanout                            ;
; t_ramdata[2]~en                        ; Lost fanout                            ;
; t_ramdata[3]~en                        ; Lost fanout                            ;
; t_ramdata[4]~en                        ; Lost fanout                            ;
; t_ramdata[5]~en                        ; Lost fanout                            ;
; t_ramdata[6]~en                        ; Lost fanout                            ;
; t_ramdata[7]~en                        ; Lost fanout                            ;
; t_dadata[3]                            ; Merged with t_dadata[0]                ;
; t_dadata[2]                            ; Merged with t_dadata[0]                ;
; t_dadata[13]                           ; Merged with t_dadata[0]                ;
; t_dadata[12]                           ; Merged with t_dadata[1]                ;
; t_dadata[14]                           ; Merged with t_dadata[1]                ;
; t_dadata[0]                            ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 14 ;                                        ;
+----------------------------------------+----------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 101   ;
; Number of registers using Synchronous Clear  ; 21    ;
; Number of registers using Synchronous Load   ; 13    ;
; Number of registers using Asynchronous Clear ; 50    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 91    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; t_adcs                                 ; 1       ;
; t_rd                                   ; 1       ;
; t_ramcs                                ; 2       ;
; Total number of inverted registers = 3 ;         ;
+----------------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 6:1                ; 3 bits    ; 12 LEs        ; 3 LEs                ; 9 LEs                  ; Yes        ; |a2d|t_dadata[15]          ;
; 6:1                ; 8 bits    ; 32 LEs        ; 8 LEs                ; 24 LEs                 ; Yes        ; |a2d|t_dadata[9]           ;
; 6:1                ; 8 bits    ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; Yes        ; |a2d|t_ramdata[7]          ;
; 6:1                ; 16 bits   ; 64 LEs        ; 16 LEs               ; 48 LEs                 ; Yes        ; |a2d|t_ramaddr[12]         ;
; 4:1                ; 10 bits   ; 20 LEs        ; 0 LEs                ; 20 LEs                 ; Yes        ; |a2d|time[3]               ;
; 15:1               ; 2 bits    ; 20 LEs        ; 4 LEs                ; 16 LEs                 ; Yes        ; |a2d|count3[1]             ;
; 20:1               ; 3 bits    ; 39 LEs        ; 3 LEs                ; 36 LEs                 ; Yes        ; |a2d|ram_part_addr[0]      ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |a2d|t_adcs                ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |a2d|comb~20               ;
; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; No         ; |a2d|comb~24               ;
; 4:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; No         ; |a2d|t_ramdata~16          ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Wed Apr 30 06:55:38 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off a2d -c a2d
Info: Found 2 design units, including 1 entities, in source file a2d.vhd
    Info: Found design unit 1: a2d-aa
    Info: Found entity 1: a2d
Info: Elaborating entity "a2d" for the top level hierarchy
Warning: Converted TRI buffer or tri-state bus to logic, or removed OPNDRN
    Warning: Converting TRI node "t_ramdata[0]~24" that feeds logic to a wire
    Warning: Converting TRI node "t_ramdata[1]~25" that feeds logic to a wire
    Warning: Converting TRI node "t_ramdata[2]~26" that feeds logic to a wire
    Warning: Converting TRI node "t_ramdata[3]~27" that feeds logic to a wire
    Warning: Converting TRI node "t_ramdata[4]~28" that feeds logic to a wire
    Warning: Converting TRI node "t_ramdata[5]~29" that feeds logic to a wire
    Warning: Converting TRI node "t_ramdata[6]~30" that feeds logic to a wire
    Warning: Converting TRI node "t_ramdata[7]~31" that feeds logic to a wire
Info: Duplicate registers merged to single register
    Info: Duplicate register "t_dadata[3]" merged to single register "t_dadata[0]"
    Info: Duplicate register "t_dadata[2]" merged to single register "t_dadata[0]"
    Info: Duplicate register "t_dadata[13]" merged to single register "t_dadata[0]"
    Info: Duplicate register "t_dadata[12]" merged to single register "t_dadata[1]"
    Info: Duplicate register "t_dadata[14]" merged to single register "t_dadata[1]"
Warning: Reduced register "t_dadata[0]" with stuck data_in port to stuck value GND
Info: Registers with preset signals will power-up high
Info: 8 registers lost all their fanouts during netlist optimizations. The first 8 are displayed below.
    Info: Register "t_ramdata[0]~en" lost all its fanouts during netlist optimizations.
    Info: Register "t_ramdata[1]~en" lost all its fanouts during netlist optimizations.
    Info: Register "t_ramdata[2]~en" lost all its fanouts during netlist optimizations.
    Info: Register "t_ramdata[3]~en" lost all its fanouts during netlist optimizations.
    Info: Register "t_ramdata[4]~en" lost all its fanouts during netlist optimizations.
    Info: Register "t_ramdata[5]~en" lost all its fanouts during netlist optimizations.
    Info: Register "t_ramdata[6]~en" lost all its fanouts during netlist optimizations.
    Info: Register "t_ramdata[7]~en" lost all its fanouts during netlist optimizations.
Info: Implemented 416 device resources after synthesis - the final resource count might be different
    Info: Implemented 12 input pins
    Info: Implemented 16 output pins
    Info: Implemented 388 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings
    Info: Allocated 140 megabytes of memory during processing
    Info: Processing ended: Wed Apr 30 06:55:49 2008
    Info: Elapsed time: 00:00:11