LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_unsigned.ALL;

ENTITY da IS
	PORT
	(
		clk                 : IN	STD_LOGIC;
		clk2                : buffer	STD_LOGIC;
		pdb1,pdb2,pdb3		: OUT	STD_LOGIC;
		data1,data2	            : out	STD_LOGIC_VECTOR(7 DOWNTO 0);
		ins                 : out   STD_LOGIC_VECTOR(2 DOWNTO 0)
	);
END da;

ARCHITECTURE a OF da IS 
------------------------------------------------------------------------
	

	SIGNAL cnt              : STD_LOGIC_VECTOR(19 DOWNTO 0);
	signal counter          : STD_LOGIC_VECTOR(7 DOWNTO 0);
	signal sign             : std_logic;

BEGIN
	
--****************************************************************
	divide_clk:PROCESS(clk)
	BEGIN 
	IF(rising_edge(clk))THEN
	IF cnt="11111111111111111111" THEN 
		cnt<="00000000000000000000";
		clk2<=not(clk2);
	ELSE cnt<=cnt+1;
	END IF;
	END IF;
	END PROCESS;
	----------------------------------------
	pdb1<='0';
	pdb2<='0';
	pdb3<='1';
	ins<="010";
	
	process(clk2)
	begin
	IF(rising_edge(clk2))THEN
	if counter="00000001" then
	sign<='0';
	end if;
	if counter="11111110" then
	sign<='1';
	end if; 
	end if;
	end process;
	
	process(clk2)
	begin
	IF(rising_edge(clk2))THEN
	if sign='0' then
	counter<=counter+1;
	end if;
	if sign ='1' then
	counter<=counter-1;
	end if;
	end if;
	end process;
	
	process(clk)
	begin
	IF(rising_edge(clk))THEN
	data1<=counter;
	data2<=counter;
	end if;
	end process;
		 
END a;