?? da.map.rpt
字號:
; Number of synthesis-generated cells ; 58 ;
; Number of WYSIWYG LUTs ; 33 ;
; Number of synthesis-generated LUTs ; 52 ;
; Number of WYSIWYG registers ; 33 ;
; Number of synthesis-generated registers ; 10 ;
; Number of cells with combinational logic only ; 48 ;
; Number of cells with registers only ; 6 ;
; Number of cells with combinational logic and registers ; 37 ;
+--------------------------------------------------------+-------+
+------------------------------------------------------+
; State Machine - |daa|state ;
+----------+----------+----------+----------+----------+
; Name ; state.s3 ; state.s2 ; state.s1 ; state.s0 ;
+----------+----------+----------+----------+----------+
; state.s0 ; 0 ; 0 ; 0 ; 0 ;
; state.s1 ; 0 ; 0 ; 1 ; 1 ;
; state.s2 ; 0 ; 1 ; 0 ; 1 ;
; state.s3 ; 1 ; 0 ; 0 ; 1 ;
+----------+----------+----------+----------+----------+
+-----------+
; Hierarchy ;
+-----------+
daa
|-- lpm_counter:cnt1_rtl_1
|-- cntr_ib7:auto_generated
|-- lpm_counter:cnt_rtl_0
|-- cntr_jb7:auto_generated
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+---------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+-----------------------------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+---------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+-----------------------------------------------------+
; |daa ; 91 (74) ; 43 ; 0 ; 24 ; 0 ; 48 (48) ; 6 (6) ; 37 (20) ; 33 (16) ; |daa ;
; |lpm_counter:cnt1_rtl_1| ; 8 (0) ; 8 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 8 (0) ; 8 (0) ; |daa|lpm_counter:cnt1_rtl_1 ;
; |cntr_ib7:auto_generated| ; 8 (8) ; 8 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 8 (8) ; 8 (8) ; |daa|lpm_counter:cnt1_rtl_1|cntr_ib7:auto_generated ;
; |lpm_counter:cnt_rtl_0| ; 9 (0) ; 9 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 9 (0) ; 9 (0) ; |daa|lpm_counter:cnt_rtl_0 ;
; |cntr_jb7:auto_generated| ; 9 (9) ; 9 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 9 (9) ; 9 (9) ; |daa|lpm_counter:cnt_rtl_0|cntr_jb7:auto_generated ;
+---------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+-----------------------------------------------------+
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/quartus/演示程序/da/da.map.eqn.
+------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+-------------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Name with Absolute Path ;
+----------------------------------+-----------------+-------------------------------------------------------------------------------------+
; daa.vhd ; yes ; F:/quartus/演示程序/da/daa.vhd ;
; lpm_counter.tdf ; yes ; d:/program files/altera/qprogrammer/libraries/megafunctions/lpm_counter.tdf ;
; lpm_constant.inc ; yes ; d:/program files/altera/qprogrammer/libraries/megafunctions/lpm_constant.inc ;
; lpm_decode.inc ; yes ; d:/program files/altera/qprogrammer/libraries/megafunctions/lpm_decode.inc ;
; lpm_add_sub.inc ; yes ; d:/program files/altera/qprogrammer/libraries/megafunctions/lpm_add_sub.inc ;
; cmpconst.inc ; yes ; d:/program files/altera/qprogrammer/libraries/megafunctions/cmpconst.inc ;
; lpm_compare.inc ; yes ; d:/program files/altera/qprogrammer/libraries/megafunctions/lpm_compare.inc ;
; lpm_counter.inc ; yes ; d:/program files/altera/qprogrammer/libraries/megafunctions/lpm_counter.inc ;
; dffeea.inc ; yes ; d:/program files/altera/qprogrammer/libraries/megafunctions/dffeea.inc ;
; alt_synch_counter.inc ; yes ; d:/program files/altera/qprogrammer/libraries/megafunctions/alt_synch_counter.inc ;
; alt_synch_counter_f.inc ; yes ; d:/program files/altera/qprogrammer/libraries/megafunctions/alt_synch_counter_f.inc ;
; alt_counter_f10ke.inc ; yes ; d:/program files/altera/qprogrammer/libraries/megafunctions/alt_counter_f10ke.inc ;
; alt_counter_stratix.inc ; yes ; d:/program files/altera/qprogrammer/libraries/megafunctions/alt_counter_stratix.inc ;
; aglobal42.inc ; yes ; d:/program files/altera/qprogrammer/libraries/megafunctions/aglobal42.inc ;
; db/cntr_jb7.tdf ; yes ; F:/quartus/演示程序/da/db/cntr_jb7.tdf ;
; db/cntr_ib7.tdf ; yes ; F:/quartus/演示程序/da/db/cntr_ib7.tdf ;
+----------------------------------+-----------------+-------------------------------------------------------------------------------------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource ; Usage ;
+-----------------------------------+---------+
; Logic cells ; 91 ;
; Total combinational functions ; 85 ;
; Total 4-input functions ; 28 ;
; Total 3-input functions ; 13 ;
; Total 2-input functions ; 28 ;
; Total 1-input functions ; 16 ;
; Total 0-input functions ; 0 ;
; Combinational cells for routing ; 0 ;
; Total registers ; 43 ;
; Total logic cells in carry chains ; 33 ;
; I/O pins ; 24 ;
; Maximum fan-out node ; cnt0[0] ;
; Maximum fan-out ; 23 ;
; Total fan-out ; 323 ;
; Average fan-out ; 2.81 ;
+-----------------------------------+---------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
Info: Processing started: Sun Aug 14 17:08:21 2005
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off da -c da
Info: Found 2 design units, including 1 entities, in source file da.vhd
Info: Found design unit 1: da-a
Info: Found entity 1: da
Info: Found 2 design units, including 1 entities, in source file da_0.vhd
Info: Found design unit 1: da_0-a
Info: Found entity 1: da_0
Info: Found 2 design units, including 1 entities, in source file daa.vhd
Info: Found design unit 1: daa-a
Info: Found entity 1: daa
Warning: VHDL Process Statement warning at daa.vhd(75): signal "counter1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at daa.vhd(81): signal "counter2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at daa.vhd(103): signal "clk1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at daa.vhd(110): signal "clk2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at daa.vhd(96): signal or variable "counter1" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "counter1" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at daa.vhd(96): signal or variable "counter2" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "counter2" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at daa.vhd(96): signal or variable "sign" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "sign" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at daa.vhd(120): signal "clk1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at daa.vhd(121): signal "counter1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at daa.vhd(122): signal "counter1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at daa.vhd(124): signal "clk2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at daa.vhd(125): signal "counter2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at daa.vhd(126): signal "counter2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Duplicate registers merged to single register
Info: Duplicate register "cnt1[0]" merged to single register "cnt0[0]"
Info: Duplicate register "cnt[0]" merged to single register "cnt0[0]"
Info: State machine "|daa|state" contains 4 states and 0 state bits
Info: Selected Auto state machine encoding method for state machine "|daa|state"
Info: Encoding result for state machine "|daa|state"
Info: Completed encoding using 4 state bits
Info: Encoded state bit "state.s3"
Info: Encoded state bit "state.s2"
Info: Encoded state bit "state.s1"
Info: Encoded state bit "state.s0"
Info: State "|daa|state.s0" uses code string "0000"
Info: State "|daa|state.s1" uses code string "0011"
Info: State "|daa|state.s2" uses code string "0101"
Info: State "|daa|state.s3" uses code string "1001"
Info: Inferred 2 megafunctions from design logic
Info: Inferred lpm_counter megafunction (LPM_WIDTH=9) from the following logic: "cnt[1]~23"
Info: Inferred lpm_counter megafunction (LPM_WIDTH=8) from the following logic: "cnt1[1]~21"
Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/qprogrammer/libraries/megafunctions/lpm_counter.tdf
Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file db/cntr_jb7.tdf
Info: Found entity 1: cntr_jb7
Info: Found 1 design units, including 1 entities, in source file db/cntr_ib7.tdf
Info: Found entity 1: cntr_ib7
Warning: Output pins are stuck at VCC or GND
Warning: Pin "pdb1" stuck at GND
Warning: Pin "pdb2" stuck at GND
Warning: Pin "pdb3" stuck at VCC
Warning: Pin "ins[2]" stuck at GND
Warning: Pin "ins[1]" stuck at VCC
Warning: Pin "ins[0]" stuck at GND
Info: Implemented 115 device resources after synthesis - the final resource count might be different
Info: Implemented 1 input pins
Info: Implemented 23 output pins
Info: Implemented 91 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 20 warnings
Info: Processing ended: Sun Aug 14 17:08:27 2005
Info: Elapsed time: 00:00:07
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