; Number of registers using Asynchronous Clear ; 18    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 18    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 18 bits   ; 36 LEs        ; 18 LEs               ; 18 LEs                 ; No         ; |reg_add|process0~35       ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/vhdl_exe/reg_add/reg_add.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Mon Aug 13 09:53:02 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off reg_add -c reg_add
Info: Found 2 design units, including 1 entities, in source file reg_add.vhd
    Info: Found design unit 1: reg_add-one
    Info: Found entity 1: reg_add
Info: Elaborating entity "reg_add" for the top level hierarchy
Warning: VHDL Process Statement warning at reg_add.vhd(59): signal "result" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at reg_add.vhd(65): signal "q0" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at reg_add.vhd(65): signal "q1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at reg_add.vhd(66): signal "q2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at reg_add.vhd(66): signal "q3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at reg_add.vhd(67): signal "q4" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at reg_add.vhd(67): signal "q5" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at reg_add.vhd(68): signal "q6" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at reg_add.vhd(68): signal "q7" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at reg_add.vhd(69): signal "q8" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at reg_add.vhd(69): signal "q9" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at reg_add.vhd(70): signal "q10" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at reg_add.vhd(71): signal "sum91" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at reg_add.vhd(71): signal "sum92" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at reg_add.vhd(72): signal "sum93" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at reg_add.vhd(72): signal "sum94" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at reg_add.vhd(73): signal "sum95" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at reg_add.vhd(73): signal "sum96" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at reg_add.vhd(74): signal "sum101" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at reg_add.vhd(74): signal "sum102" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at reg_add.vhd(74): signal "sum103" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at reg_add.vhd(75): signal "result" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at reg_add.vhd(75): signal "sum104" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at reg_add.vhd(52): signal or variable "sum" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "sum" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at reg_add.vhd(52): signal or variable "data_yn" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "data_yn" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at reg_add.vhd(52): signal or variable "flag" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "flag" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at reg_add.vhd(52): signal or variable "sum91" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "sum91" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at reg_add.vhd(52): signal or variable "sum92" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "sum92" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at reg_add.vhd(52): signal or variable "sum93" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "sum93" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at reg_add.vhd(52): signal or variable "sum94" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "sum94" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at reg_add.vhd(52): signal or variable "sum95" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "sum95" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at reg_add.vhd(52): signal or variable "sum96" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "sum96" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at reg_add.vhd(52): signal or variable "sum101" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "sum101" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at reg_add.vhd(52): signal or variable "sum102" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "sum102" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at reg_add.vhd(52): signal or variable "sum103" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "sum103" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at reg_add.vhd(52): signal or variable "sum104" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "sum104" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Reduced register "result[0]" with stuck data_in port to stuck value GND
Warning: Latch flag$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal clk_reg
Warning: Latch data_yn[0]$latch has unsafe behavior
    Warning: Ports ENA and CLR on the latch are fed by the same signal process0~0
Warning: Latch data_yn[1]$latch has unsafe behavior
    Warning: Ports ENA and CLR on the latch are fed by the same signal process0~0
Warning: Latch data_yn[2]$latch has unsafe behavior
    Warning: Ports ENA and CLR on the latch are fed by the same signal process0~0
Warning: Latch data_yn[3]$latch has unsafe behavior
    Warning: Ports ENA and CLR on the latch are fed by the same signal process0~0
Warning: Latch data_yn[4]$latch has unsafe behavior
    Warning: Ports ENA and CLR on the latch are fed by the same signal process0~0
Warning: Latch data_yn[5]$latch has unsafe behavior
    Warning: Ports ENA and CLR on the latch are fed by the same signal process0~0
Warning: Latch data_yn[6]$latch has unsafe behavior
    Warning: Ports ENA and CLR on the latch are fed by the same signal process0~0
Warning: Latch data_yn[7]$latch has unsafe behavior
    Warning: Ports ENA and CLR on the latch are fed by the same signal process0~0
Warning: Latch sum[10] has unsafe behavior
    Warning: Ports ENA and CLR on the latch are fed by the same signal process0~0
Warning: Latch sum[11] has unsafe behavior
    Warning: Ports ENA and CLR on the latch are fed by the same signal process0~0
Warning: Latch sum[12] has unsafe behavior
    Warning: Ports ENA and CLR on the latch are fed by the same signal process0~0
Warning: Latch sum[13] has unsafe behavior
    Warning: Ports ENA and CLR on the latch are fed by the same signal process0~0
Warning: Latch sum[14] has unsafe behavior
    Warning: Ports ENA and CLR on the latch are fed by the same signal process0~0
Warning: Latch sum[15] has unsafe behavior
    Warning: Ports ENA and CLR on the latch are fed by the same signal process0~0
Warning: Latch sum[16] has unsafe behavior
    Warning: Ports ENA and CLR on the latch are fed by the same signal process0~0
Warning: Latch sum[17] has unsafe behavior
    Warning: Ports ENA and CLR on the latch are fed by the same signal process0~0
Warning: Latch sum[9] has unsafe behavior
    Warning: Ports ENA and CLR on the latch are fed by the same signal process0~0
Warning: Latch sum[8] has unsafe behavior
    Warning: Ports ENA and CLR on the latch are fed by the same signal process0~0
Warning: Latch sum[7] has unsafe behavior
    Warning: Ports ENA and CLR on the latch are fed by the same signal process0~0
Warning: Latch sum[6] has unsafe behavior
    Warning: Ports ENA and CLR on the latch are fed by the same signal process0~0
Warning: Latch sum[5] has unsafe behavior
    Warning: Ports ENA and CLR on the latch are fed by the same signal process0~0
Warning: Latch sum[4] has unsafe behavior
    Warning: Ports ENA and CLR on the latch are fed by the same signal process0~0
Warning: Latch sum[3] has unsafe behavior
    Warning: Ports ENA and CLR on the latch are fed by the same signal process0~0
Warning: Latch sum[2] has unsafe behavior
    Warning: Ports ENA and CLR on the latch are fed by the same signal process0~0
Warning: Latch sum[1] has unsafe behavior
    Warning: Ports ENA and CLR on the latch are fed by the same signal process0~0
Warning: Latch sum[0] has unsafe behavior
    Warning: Ports ENA and CLR on the latch are fed by the same signal process0~0
Info: Implemented 361 device resources after synthesis - the final resource count might be different
    Info: Implemented 92 input pins
    Info: Implemented 9 output pins
    Info: Implemented 260 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 91 warnings
    Info: Processing ended: Mon Aug 13 09:53:05 2007
    Info: Elapsed time: 00:00:03