GAS LISTING /tmp/ccxobHen.s 			page 1   1              	# 1 "/mnt/hgfs/boot/booter/source/reset.S"   2              	# 1 "/mnt/hgfs/boot/booter/source//"   1              	   1              	...   0              	   0              	   2              			.section ".reset"   3              			.text   4              			.global	reset   5              	reset:   6              	/*   7              	shuaiwen:direct jump to start address,just fit for run in sdram   8              	*/   9 0000 7B010010 		b resetsdram   9      00000000   10              	#include "reset.h"   1              	#include "platform.h"   1              	#ifndef DB1200   2              	#define DB1200   2              	   3              	#ifdef PB1000   4              		#include "../platforms/PB1000/reset_pb1100.S"   5              	#endif   6              	   7              	#ifdef PB1100   8              		#include "../platforms/PB1100/reset_pb1100.S"   9              	#endif  10              	  11              	#ifdef PB1200  12              		#include "../platforms/PB1200/reset_pb1200.S"  13              	#endif  14              	  15              	#ifdef PB1500  16              		#include "../platforms/PB1500/reset_pb1500.S"  17              	#endif  18              	  19              	#ifdef PB1550  20              		#include "../platforms/PB1550/reset_pb1550.S"  21              	#endif  22              	  23              	#ifdef DB1000  24              		#include "../platforms/DB1000/reset_db1000.S"  25              	#endif  26              	  27              	#ifdef DB1100  28              		#include "../platforms/DB1100/reset_db1100.S"  29              	#endif  30              	  31              	#ifdef DB1200  32              		#include "../platforms/DB1200/reset_db1200.S"   1              	/*********************************************************************   2              	 *   3              	 * Copyright:   4              	 *	Advanced Micro Devices, AMD. All Rights Reserved.     5              	 *  You are hereby granted a copyright license to use, modify, and   6              	 *  distribute the SOFTWARE so long as this entire notice is   7              	 *  retained without alteration in any modified and/or redistributedGAS LISTING /tmp/ccxobHen.s 			page 2   8              	 *  versions, and that such modified versions are clearly identified   9              	 *  as such. No licenses are granted by implication, estoppel or  10              	 *  otherwise under any patents or trademarks of AMD. This   11              	 *  software is provided on an "AS IS" basis and without warranty.  12              	 *  13              	 *  To the maximum extent permitted by applicable law, AMD   14              	 *  DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING   15              	 *  IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR  16              	 *  PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE   17              	 *  SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY   18              	 *  ACCOMPANYING WRITTEN MATERIALS.  19              	 *   20              	 *  To the maximum extent permitted by applicable law, IN NO EVENT  21              	 *  SHALL AMD BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING   22              	 *  WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS   23              	 *  INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY  24              	 *  LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.     25              	 *   26              	 *  AMD assumes no responsibility for the maintenance and support  27              	 *  of this software.  28              	 ********************************************************************/  29              	  30              	/*  31              	  32              	This file represents all the activities necessary to bring  33              	the Au1200 out of reset. It sets all Au1200 resources to  34              	known, usually disabled and safe, state.  35              	  36              	This is an example startup file, tailored for the DBAu1200  37              	reference board. DBAu1200-specific items are commented as  38              	such, but in general are confined to the CPU endian  39              	selection and memory controller values.  40              	  41              	*/  42              	  43              	  44              	/********************************************************************/  45              	  46              	/*  47              	 * MIPS ABI register defintions  48              	 */  49              	#define zero		$0  50              	#define v0		$2  51              	#define v1		$3  52              	#define a0		$4  53              	#define a1		$5  54              	#define a2		$6  55              	#define a3		$7  56              	#define t0		$8  57              	#define t1		$9  58              	#define t2		$10  59              	#define t3		$11  60              	#define t4		$12  61              	#define t5		$13  62              	#define t6		$14  63              	#define t7		$15  64              	#define s0		$16GAS LISTING /tmp/ccxobHen.s 			page 3  65              	#define s1		$17  66              	#define s2		$18  67              	#define s3		$19  68              	#define s4		$20  69              	#define s5		$21  70              	#define s6		$22  71              	#define s7		$23  72              	#define t8		$24  73              	#define t9		$25  74              	#define k0		$26  75              	#define k1		$27  76              	#define gp		$28  77              	#define sp		$29  78              	#define fp		$30  79              	#define ra		$31  80              	  81              	/********************************************************************/  82              	  83              	/*  84              	 * Au1200 CP0 registers  85              	 */  86              	#define CP0_Index		$0  87              	#define CP0_Random		$1  88              	#define CP0_EntryLo0	$2  89              	#define CP0_EntryLo1	$3  90              	#define CP0_Context		$4  91              	#define CP0_PageMask	$5  92              	#define CP0_Wired		$6  93              	#define CP0_BadVAddr	$8  94              	#define CP0_Count		$9  95              	#define CP0_EntryHi		$10  96              	#define CP0_Compare		$11  97              	#define CP0_Status		$12  98              	#define CP0_Cause		$13  99              	#define CP0_EPC		$14 100              	#define CP0_PRId		$15 101              	#define CP0_Config		$16 102              	#define CP0_Config0		$16 103              	#define CP0_Config1		$16,1 104              	#define CP0_LLAddr		$17 105              	#define CP0_WatchLo		$18 106              	#define CP0_IWatchLo	$18,1 107              	#define CP0_WatchHi		$19 108              	#define CP0_IWatchHi	$19,1 109              	#define CP0_Scratch		$22 110              	#define CP0_Debug		$23 111              	#define CP0_DEPC		$24 112              	#define CP0_PerfCnt		$25 113              	#define CP0_PerfCtrl	$25,1 114              	#define CP0_DTag		$28 115              	#define CP0_DData		$28,1 116              	#define CP0_ITag		$29 117              	#define CP0_IData		$29,1 118              	#define CP0_ErrorEPC	$30 119              	#define CP0_DESave		$31 120              	 121              	/********************************************************************/GAS LISTING /tmp/ccxobHen.s 			page 4 122              	 123              	/* 124              	 * Au1200 base addresses (in KSEG1 region) 125              	 */ 126              	#define AU1200_MEM_ADDR		0xB4000000 127              	#define AU1200_MAEBE_ADDR		0xB4010000 128              	#define AU1200_MAEFE_ADDR		0xB4012000 129              	#define AU1200_DDMA_ADDR		0xB4003000 130              	#define AU1200_USB_ADDR		0xB4020000 131              	#define AU1200_OTG_ADDR		0xB4020020 132              	#define AU1200_OHC_ADDR		0xB4020100 133              	#define AU1200_EHC_ADDR		0xB4020200 134              	#define AU1200_DEV_ADDR		0xB4022000 135              	#define AU1200_CIM_ADDR		0xB4004000 136              	#define AU1200_LCD_ADDR		0xB5000000 137              	#define AU1200_IC0_ADDR		0xB0400000 138              	#define AU1200_UART0_ADDR		0xB1100000 139              	#define AU1200_UART1_ADDR		0xB1200000 140              	#define AU1200_SWC_ADDR		0xB1100100 141              	#define AU1200_GPIO2_ADDR		0xB1700000 142              	#define AU1200_IC1_ADDR		0xB1800000 143              	#define AU1200_SYS_ADDR		0xB1900000 144              	#define AU1200_PSC0_ADDR		0xB1A00000 145              	#define AU1200_PSC1_ADDR		0xB1B00000 146              	#define AU1200_AES_ADDR		0xB0300000 147              	#define AU1200_SD0_ADDR		0xB0600000 148              	#define AU1200_SD1_ADDR		0xB0680000 149              	 150              	 151              	/* 152              	 * Au1200 memory controller register offsets 153              	 */ 154              	#define mem_sdmode0	    		0x0800 155              	#define mem_sdmode1	    		0x0808 156              	#define mem_sdaddr0    		0x0820 157              	#define mem_sdaddr1    		0x0828 158              	#define mem_sdconfiga		0x0840 159              	#define mem_sdconfigb		0x0848 160              	#define mem_sdstat			0x0850 161              	#define mem_sdwrmd0 		0x0880 162              	#define mem_sdwrmd1 		0x0888 163              	#define mem_sdprecmd		0x08C0 164              	#define mem_sdautoref		0x08C8 165              	#define mem_sdsref			0x08D0 166              	 167              	#define mem_stcfg0			0x1000 168              	#define mem_sttime0			0x1004 169              	#define mem_staddr0			0x1008 170              	#define mem_stcfg1			0x1010 171              	#define mem_sttime1			0x1014 172              	#define mem_staddr1			0x1018 173              	#define mem_stcfg2			0x1020 174              	#define mem_sttime2			0x1024 175              	#define mem_staddr2			0x1028 176              	#define mem_stcfg3			0x1030 177              	#define mem_sttime3			0x1034 178              	#define mem_staddr3			0x1038GAS LISTING /tmp/ccxobHen.s 			page 5 179              	#define mem_staltime		0x1040 180              	#define mem_stndctrl		0x1100 181              	 182              	 183              	/* 184              	 * Au1200 peripheral register offsets 185              	 */ 186              	#define ddma_inten			0x000C 187              	#define psc_enable			0x0004		 188              	#define uart_enable			0x0100 189              	#define maebe_ctlenable		0x0700 190              	#define cim_enable			0x0000 191              	#define lcd_screen			0x0004 192              	#define swcnt_control		0x0000 193              	#define usb_cfg			0x0004 194              	#define sd_enable			0x000C 195              	#define aes_status			0x0000 196              	 197              	#define ic_cfg0clr			0x0044 198              	#define ic_cfg1clr			0x004C 199              	#define ic_cfg2clr			0x0054 200              	#define ic_srcset			0x0058 201              	#define ic_assignset		0x0060 202              	#define ic_wakeclr			0x006C 203              	#define ic_maskclr			0x0074 204              	#define ic_risingclr		0x0078 205              	#define ic_fallingclr		0x007C 206              	#define ic_testbit			0x0080 207              	 208              	#define sys_scratch0		0x0018 209              	#define sys_scratch1		0x001c 210              	#define sys_cntctrl			0x0014 211              	#define sys_freqctrl0		0x0020 212              	#define sys_freqctrl1		0x0024 213              	#define sys_clksrc			0x0028 214              	#define sys_pinfunc			0x002C 215              	#define sys_wakemsk			0x0034 216              	#define sys_powerctrl		0x003C 217              	#define sys_endian			0x0038 218              	#define sys_wakesrc			0x005C 219              	#define sys_cpupll			0x0060 220              	#define sys_auxpll			0x0064 221              	#define sys_trioutclr		0x0100 222              	#define sys_outputset		0x0108 223              	#define sys_outputclr		0x010C 224              	#define sys_pininputen		0x0110 225              	 226              	#define gpio2_dir			0x0000 227              	#define gpio2_output		0x0008 228              	#define gpio2_pinstate		0x000C 229              	#define gpio2_inten			0x0010 230              	#define gpio2_enable		0x0014 231              	 232              	 233              	/********************************************************************/ 234              	 235              	/*GAS LISTING /tmp/ccxobHen.s 			page 6 236              	 * DBAu1200-specific values 237              	 * NOTE: All values are for operation at 396MHz, SD=2 238              	 */ 239              	 240              	//#define SYS_CPUPLL		28	/* 336Mhz */ 241              	#define SYS_CPUPLL		33	/* 396Mhz */ 242              	#define SYS_POWERCTRL	0	/* SD=2 */ 243              	#define SYS_AUXPLL		0	/* disable */ 244              	 245              	/* 246              	 * With SBUS of 198MHz and mem_stcfg0[TS]=0, static bus controller 247              	 * clock period is 5ns 248              	 */ 249              	 250              	/* Address Latch Timing - SN74LVC16374ADVG latch on rising edge of ALE 251              	  Tah=000 (0   clocks) 252              	  Tlw=000 (1+0 clocks) 253              	 Tasu=001 (1   clocks) Latch needs 3ns 254              	 */ 255              	#define MEM_STALTIME 0x00000001 256              	 257              	/* RCE0: 120ns x16 Nor Flash 258              	 259              	 Tcsoe= (1+0  clocks) data sheet specs MAX(tCE 120ns - tOE 25ns), choose 5ns for stable address, AS 260              	 Toecs= (0+0  clocks) data sheet specs   0ns, AH=0 261              	  Twcs= (1+0  clocks) data sheet specs   0ns for tCH 262              	  Tcsh= (1+6  clocks) data sheet specs MAX(tWPH 30ns, tCEH 35ns)