GAS LISTING /tmp/ccxobHen.s 			page 12 578              		/* 579              		 * Step 3) Establish CP0 Config0 580              		 * (set OD, set K0=3) 581              		 */ 582 0030 0800093C 		li	t1, 0x00080003 582      03002935  583 0038 00808940 		mtc0	t1, CP0_Config0 584              	 585              		/* 586              		 * Step 4) Disable Watchpoint facilities 587              		 */ 588 003c 00000924 		li	t1, 0x00000000 589 0040 00908940 		mtc0	t1, CP0_WatchLo 590 0044 01908940 		mtc0	t1, CP0_IWatchLo 591              	 592              		/* 593              		 * Step 5) Disable the performance counters 594              		 */ 595 0048 01C88040 		mtc0	zero, CP0_PerfCtrl 596 004c 00000000 		nop 597              	 598              		/* 599              		 * Step 6) Establish EJTAG Debug register 600              		 */ 601 0050 00B88040 		mtc0	zero, CP0_Debug 602 0054 00000000 		nop 603              	 604              		/* 605              		 * Step 7) Establish Cause 606              		 * (set IV bit) 607              		 */ 608 0058 8000093C 		li	t1, 0x00800000 609 005c 00688940 		mtc0	t1, CP0_Cause 610              	 611              		/* 612              		 * Step 8) Initialize the caches 613              		 */ 614 0060 00400824 		li	t0, (16*1024) 615 0064 20000924 		li	t1, 32 616 0068 00800A3C 		li	t2, 0x80000000 617 006c 21580A01 		addu	t3, t0, t2 618              	cacheloop: 619 0070 000040BD 		cache	0, 0(t2) 620 0074 000041BD 		cache	1, 0(t2) 621 0078 21504901 		addu	t2, t1 622 007c FCFF4B15 		bne	t2, t3, cacheloop 623 0080 00000000 		nop 624              	 625              		/* Run from cacheable space now */ 626 0084 01001104 		bal	cachehere 627 0088 00000000 		nop 628              	cachehere: 629 008c FFDF093C 		li	t1, ~0x20000000 /* convert to KSEG0 */ 629      FFFF2935  630 0094 2440E903 		and	t0, ra, t1 631 0098 14000821 		addi	t0, 5*4			/* 5 insns beyond cachehere */ 632 009c 08000001 		jr	t0GAS LISTING /tmp/ccxobHen.s 			page 13 633 00a0 00000000 		nop 634              	 635              		/* 636              		 * Step 9) Initialize the TLB 637              		 */ 638 00a4 00000824 		li	t0, 0		 	# index value 639 00a8 00000924 		li	t1, 0x00000000 	# entryhi value 640 00ac 20000A24 		li	t2, 32		   	# 32 entries 641              	tlbloop: 642              		/* Probe TLB for matching EntryHi */ 643 00b0 00508940 		mtc0	t1, CP0_EntryHi 644 00b4 08000042 		tlbp 645 00b8 00000000 		nop 646              	 647              		/* Examine Index[P], 1=no matching entry */ 648 00bc 00000B40 		mfc0	t3, CP0_Index 649 00c0 00800C3C 		li	t4, 0x80000000 650 00c4 24588B01 		and	t3, t4, t3 651 00c8 01002925 		addiu	t1, t1, 1		# increment t1 (asid) 652 00cc F8FF0B10 		beq	zero, t3, tlbloop 653 00d0 00000000 		nop 654              	 655              		/* Initialize the TLB entry */ 656 00d4 00008840 		mtc0	t0, CP0_Index 657 00d8 00108040 		mtc0	zero, CP0_EntryLo0 658 00dc 00188040 		mtc0	zero, CP0_EntryLo1 659 00e0 00288040 		mtc0	zero, CP0_PageMask 660 00e4 02000042 		tlbwi 661              	 662              		/* Do it again */ 663 00e8 01000825 		addiu	t0, t0, 1	 664 00ec F0FF0A15 		bne	t0, t2, tlbloop 665 00f0 00000000 		nop 666              	 667              		/* Establish Wired (and Random) */ 668 00f4 00308040 		mtc0	zero, CP0_Wired 669 00f8 00000000 		nop 670              	 671              		/* 672              		 * Step 10) Establish CPU PLL frequency 673              		 */ 674 00fc 90B1083C 		li	t0, AU1200_SYS_ADDR 675 0100 21000924 		li	t1, SYS_CPUPLL 676 0104 600009AD 		sw	t1, sys_cpupll(t0) 677 0108 0F000000 		sync 678 010c 00000000 		nop 679 0110 00000000 		nop 680              	 681              		/* 682              		 * Step 11) Establish system bus divider 683              		 */ 684 0114 00000924 		li	t1, SYS_POWERCTRL 685 0118 3C0009AD 		sw	t1, sys_powerctrl(t0) 686 011c 0F000000 		sync 687              	 688              		/* 689              		 * Step 12) Establish AUX PLL frequencyGAS LISTING /tmp/ccxobHen.s 			page 14 690              		 */ 691 0120 90B1083C 		li	t0, AU1200_SYS_ADDR 692 0124 00000924 		li	t1, SYS_AUXPLL 693 0128 640009AD 		sw	t1, sys_auxpll(t0) 694 012c 0F000000 		sync 695              	 696              		/* 697              		 * Step 13) Start the 32kHz oscillator 698              		 */ 699 0130 00010924 		li	t1, 0x00000100 700 0134 140009AD 		sw	t1, sys_cntctrl(t0) 701 0138 0F000000 		sync 702              	 703              		/* 704              		 * Step 14) Initialize static memory controller 705              		 */ 706 013c 00B4083C 		li	t0, AU1200_MEM_ADDR 707 0140 2D00093C 		li	t1, MEM_STCFG0 707      43002935  708 0148 61060A3C 		li	t2, MEM_STTIME0 708      D7814A35  709 0150 C0110B3C 		li	t3, MEM_STADDR0 709      003F6B35  710 0158 001009AD 		sw	t1, mem_stcfg0(t0) 711 015c 04100AAD 		sw	t2, mem_sttime0(t0) 712 0160 08100BAD 		sw	t3, mem_staddr0(t0) 713 0164 0F000000 		sync 714              	 715              		/* RCE1 */ 716 0168 4200093C 		li	t1, MEM_STCFG1 716      45002935  717 0170 74770A24 		li	t2, MEM_STTIME1 718 0174 00120B3C 		li	t3, MEM_STADDR1 718      FF3F6B35  719 017c 101009AD 		sw	t1, mem_stcfg1(t0) 720 0180 14100AAD 		sw	t2, mem_sttime1(t0) 721 0184 18100BAD 		sw	t3, mem_staddr1(t0) 722              	 723              		/* RCE2 */ 724 0188 2D86093C 		li	t1, MEM_STCFG2 724      C6002935  725 0190 43140A3C 		li	t2, MEM_STTIME2 725      124C4A35  726 0198 80110B3C 		li	t3, MEM_STADDR2 726      003F6B35  727 01a0 201009AD 		sw	t1, mem_stcfg2(t0) 728 01a4 24100AAD 		sw	t2, mem_sttime2(t0) 729 01a8 28100BAD 		sw	t3, mem_staddr2(t0) 730              	 731              		/* RCE3 */ 732 01ac 0400093C 		li	t1, MEM_STCFG3 732      42002935  733 01b4 0E280A3C 		li	t2, MEM_STTIME3 733      073E4A35  734 01bc 00100B3C 		li	t3, MEM_STADDR3 735 01c0 301009AD 		sw	t1, mem_stcfg3(t0) 736 01c4 34100AAD 		sw	t2, mem_sttime3(t0)GAS LISTING /tmp/ccxobHen.s 			page 15 737 01c8 38100BAD 		sw	t3, mem_staddr3(t0) 738              	 739              		/* Address latch time */ 740 01cc 01000924 		li	t1, MEM_STALTIME 741 01d0 401009AD 		sw	t1, mem_staltime(t0) 742 01d4 0F000000 		sync 743              	 744              		/* NAND */ 745 01d8 001100AD 		sw	zero, mem_stndctrl(t0) 746 01dc 0F000000 		sync 747              	 748              		/* 749              		 * Step 15) Set peripherals to a known state 750              		 */ 751 01e0 40B0083C 		li	t0, AU1200_IC0_ADDR 752 01e4 FFFF0924 		li	t1, 0xFFFFFFFF 753 01e8 440009AD 		sw	t1, ic_cfg0clr(t0) 754 01ec 4C0009AD 		sw	t1, ic_cfg1clr(t0) 755 01f0 540009AD 		sw	t1, ic_cfg2clr(t0) 756 01f4 580009AD 		sw	t1, ic_srcset(t0) 757 01f8 600009AD 		sw	t1, ic_assignset(t0) 758 01fc 6C0009AD 		sw	t1, ic_wakeclr(t0) 759 0200 740009AD 		sw	t1, ic_maskclr(t0) 760 0204 780009AD 		sw	t1, ic_risingclr(t0) 761 0208 7C0009AD 		sw	t1, ic_fallingclr(t0) 762 020c 800000AD 		sw	zero, ic_testbit(t0) 763 0210 0F000000 		sync 764              	 765 0214 80B1083C 		li	t0, AU1200_IC1_ADDR 766 0218 FFFF0924 		li	t1, 0xFFFFFFFF 767 021c 440009AD 		sw	t1, ic_cfg0clr(t0) 768 0220 4C0009AD 		sw	t1, ic_cfg1clr(t0) 769 0224 540009AD 		sw	t1, ic_cfg2clr(t0) 770 0228 580009AD 		sw	t1, ic_srcset(t0) 771 022c 600009AD 		sw	t1, ic_assignset(t0) 772 0230 6C0009AD 		sw	t1, ic_wakeclr(t0) 773 0234 740009AD 		sw	t1, ic_maskclr(t0) 774 0238 780009AD 		sw	t1, ic_risingclr(t0) 775 023c 7C0009AD 		sw	t1, ic_fallingclr(t0) 776 0240 800000AD 		sw	zero, ic_testbit(t0) 777 0244 0F000000 		sync 778              	 779 0248 90B1083C 		li	t0, AU1200_SYS_ADDR 780 024c 200000AD 		sw	zero, sys_freqctrl0(t0) 781 0250 240000AD 		sw	zero, sys_freqctrl1(t0) 782 0254 280000AD 		sw	zero, sys_clksrc(t0) 783 0258 7E00093C 		li	t1, 0x007E303F 783      3F302935  784 0260 2C0009AD 		sw	t1, sys_pinfunc(t0) 785 0264 FFFF0924 		li	t1, 0xFFFFFFFF 786 0268 000109AD 		sw	t1, sys_trioutclr(t0) 787 026c 100100AD 		sw	zero, sys_pininputen(t0) 788 0270 0F000000 		sync 789              	 790 0274 70B1083C 		li	t0, AU1200_GPIO2_ADDR 791 0278 02000924 		li	t1,2 792 027c 140009AD 		sw	t1,gpio2_enable(t0)GAS LISTING /tmp/ccxobHen.s 			page 16 793              	 794 0280 00B4083C 		li	t0, AU1200_DDMA_ADDR 794      00300835  795 0288 0C0000AD 		sw	zero, ddma_inten(t0) 796              	 797 028c 10B1083C 	  	li	t0, AU1200_UART0_ADDR 798 0290 000100AD 		sw	zero, uart_enable(t0) 799              	 800 0294 20B1083C 		li	t0, AU1200_UART1_ADDR 801 0298 000100AD 		sw	zero, uart_enable(t0) 802              	 803 029c A0B1083C 		li	t0, AU1200_PSC0_ADDR 804 02a0 040000AD 		sw	zero, psc_enable(t0) 805              	 806 02a4 B0B1083C 		li	t0, AU1200_PSC1_ADDR 807 02a8 040000AD 		sw	zero, psc_enable(t0) 808              	 809 02ac 02B4083C 		li	t0, AU1200_USB_ADDR 810 02b0 D000093C 		li	t1, 0x00D02000 810      00202935  811 02b8 040009AD 		sw	t1, usb_cfg(t0) 812              	 813 02bc 00B5083C 		li	t0, AU1200_LCD_ADDR 814 02c0 040000AD 		sw	zero, lcd_screen(t0) 815              	 816 02c4 60B0083C 		li	t0, AU1200_SD0_ADDR 817 02c8 0C0000AD 		sw	zero, sd_enable(t0) 818              	 819 02cc 68B0083C 		li	t0, AU1200_SD1_ADDR 820 02d0 0C0000AD 		sw	zero, sd_enable(t0) 821              	 822 02d4 10B1083C 		li	t0, AU1200_SWC_ADDR 822      00010835  823 02dc 000000AD 		sw	zero, swcnt_control(t0) 824              	 825 02e0 30B0083C 		li	t0, AU1200_AES_ADDR 826 02e4 000000AD 		sw	zero, aes_status(t0) 827              	 828 02e8 00B4083C 		li	t0, AU1200_CIM_ADDR 828      00400835  829 02f0 000000AD 		sw	zero, cim_enable(t0) 830 02f4 0F000000 		sync 831              	 832              	 833              		/* 834              		 * Step 16) Determine cause of reset 835              		 */ 836              		/* wait 10mS to debounce external signals */ 837 02f8 3C00093C 		li	t1, MEM_1MS*10 837      C06C2935  838 0300 FFFF2921 	1:	addi	t1, t1, -1 839 0304 FEFF2015 		bne	t1, zero, 1b 840 0308 00000000 		nop 841              	 842 030c 90B1083C 		li	t0, AU1200_SYS_ADDR 843 0310 5C00098D 		lw	t1, sys_wakesrc(t0) 844              	GAS LISTING /tmp/ccxobHen.s 			page 17 845              		/* Clear sys_wakemsk to prevent false events */ 846 0314 340000AD 		sw	zero, sys_wakemsk(t0) 847 0318 0F000000 		sync 848              	 849              		/* Clear sys_wakesrc */ 850              		//sw	zero, sys_wakesrc(t0) 851              		//sync 852              	 853              		/* Check for Hibernate Reset first */ 854 031c 04002A31 		andi	t2, t1, 0x04 855 0320 09000A14 		bne	zero, t2, hibernatereset 856 0324 00000000 		nop 857              	 858              		/* Check for Hardware Reset */ 859 0328 01002A31 		andi	t2, t1, 0x01 860 032c 06000A14 		bne	zero, t2, hardwarereset 861 0330 00000000 		nop 862              	 863              		/* Check for Sleep Wakeup */ 864 0334 02002A31 		andi	t2, t1, 0x02 865 0338 09000A14 		bne	zero, t2, sleepwakeup 866 033c 00000000 		nop 867              	 868              		/* Assume run-time reset */ 869 0340 01000010 		b	runtimereset 870 0344 00000000 		nop 871