/******************************************************************************
**
**  COPYRIGHT (C) 2000, 2001 Intel Corporation.
**
**  This software as well as the software described in it is furnished under 
**  license and may only be used or copied in accordance with the terms of the 
**  license. The information in this file is furnished for informational use 
**  only, is subject to change without notice, and should not be construed as 
**  a commitment by Intel Corporation. Intel Corporation assumes no 
**  responsibility or liability for any errors or inaccuracies that may appear 
**  in this document or any software that may be provided in association with 
**  this document. 
**  Except as permitted by such license, no part of this document may be 
**  reproduced, stored in a retrieval system, or transmitted in any form or by 
**  any means without the express written consent of Intel Corporation. 
**
**  FILENAME:      xsdma.h
**
**  PURPOSE:       Contains module private declarations and definitions for 
**                 the DMA controller.
**
**  LAST MODIFIED: $Modtime: 7/17/03 1:01p $
******************************************************************************/


#ifndef C_DMA_CONTROLLER
#define C_DMA_CONTROLLER
/*
*******************************************************************************
    Error sub-location codes for ERR_L_XSDMA location code
*******************************************************************************
*/

#define ERR_S_DMA_REG_HANDLER    0x01 // XsDmaRegisterHandler
#define ERR_S_DMA_UNR_HANDLER    0x02 // XsDmaUnregisterHandler
#define ERR_S_DMA_INT_HANDLER    0x03 // XsDmaInterruptHandler
#define ERR_S_DMA_HWSETUP        0x04 // XsDmaHWSetup
#define ERR_S_DMA_START          0x05 // XsDmaStart
#define ERR_S_DMA_UNTIL_STOPPED  0x06 // XsDmaWaitUntilStopped() 
#define ERR_S_DMA_DESTROY_LINK   0x07 // XsDmaDestroyLink() 
#define ERR_S_DMA_INT_REASON_EN  0x08 // XsDmaIntReasonEnable()
#define ERR_S_DMA_RANGE_CHANNEL  0x09 // XsDmaRangeCheckChannel()
#define ERR_S_DMA_BACK_LINKS     0x0A // XsDmaMakeBackLinksInChain()
#define ERR_S_DMA_BARE_DESC      0x0B // XsDmaCreateBareDescChain()
#define ERR_S_DMA_POPULATE_DESC  0x0C // XsDmaPopulateDescWithBufs()
#define ERR_S_DMA_POPULATE_CHAIN 0x0D // XsDmaPopulateChainWithBufs()
#define ERR_S_DMA_DESCR_CHAIN    0x0E // XsDmaCreateDescriptorFromChan()
#define ERR_S_DMA_CONFIG_DEVICE  0x0F // XsDmaConfigureDevice()
#define ERR_S_DMA_CONFIG_MEM     0x10 // XsDmaConfigureMemToMem()

/*
*******************************************************************************
Structure for channels and the relative priority. 
*******************************************************************************
*/
typedef struct XsDmaChannelPrioritySearchEntryS
{
    UINT channel;
    XsDmaChannelPriorityT priority;
}XsDmaChannelPrioritySearchEntryT;

/*
*******************************************************************************
This is a structure of DMA register groups that will make accesses more easily
through simple program control instead of long-winded switch constructs.
*******************************************************************************
*/

typedef struct XsDmaDescriptorGroupS {
    VUINT   DDADR;  // descriptor address reg
    VUINT   DSADR;  // source address register
    VUINT   DTADR;  // target address register
    VUINT   DCMD;   // command address register
}XsDmaDescriptorGroupT;

/*
*******************************************************************************
    XsDmaDrcmrIdT for indexing the DRCMR registers.
*******************************************************************************
*/

typedef enum XsDmaDrcmrIdE
{
    XSDMA_DRCMR_ID_DREQ_0         =   0, // companion chip request 0
    XSDMA_DRCMR_ID_DREQ_1         =   1, // companion chip request 1
    XSDMA_DRCMR_ID_I2S_RX         =   2, // I2S receive request
    XSDMA_DRCMR_ID_I2S_TX         =   3, // I2S transmit request
    XSDMA_DRCMR_ID_BTUART_RX      =   4, // BTUART receive request
    XSDMA_DRCMR_ID_BTUART_TX      =   5, // BTUART transmit request
    XSDMA_DRCMR_ID_FFUART_RX      =   6, // FFUART receive request
    XSDMA_DRCMR_ID_FFUART_TX      =   7, // FFUART transmit request
    XSDMA_DRCMR_ID_AC97_MIC_RX    =   8, // AC97 microphone request
    XSDMA_DRCMR_ID_AC97_MODEM_RX  =   9, // AC97 MODEM receive request
    XSDMA_DRCMR_ID_AC97_MODEM_TX  =   10, // AC97 MODEM transmit request
    XSDMA_DRCMR_ID_AC97_AUDIO_RX  =   11, // AC97 Audio receive request
    XSDMA_DRCMR_ID_AC97_AUDIO_TX  =   12, // AC97 Audio transmit request
    XSDMA_DRCMR_ID_SSP1_RX        =   13, // SSP receive request
    XSDMA_DRCMR_ID_SSP1_TX        =   14, // SSP transmit request
    XSDMA_DRCMR_ID_SSP2_RX        =   15, // SSP2 receive request
    XSDMA_DRCMR_ID_SSP2_TX        =   16, // SSP2 transmit request
    XSDMA_DRCMR_ID_FICP_RX        =   17, // ICP receive request
    XSDMA_DRCMR_ID_FICP_TX        =   18, // ICP transmit request
    XSDMA_DRCMR_ID_STUART_RX      =   19, // STUART receive request
    XSDMA_DRCMR_ID_STUART_TX      =   20, // STUART transmit request
    XSDMA_DRCMR_ID_MMC_RX         =   21, // MMC receive request
    XSDMA_DRCMR_ID_MMC_TX         =   22, // MMC transmit request
    XSDMA_DRCMR_ID_RSVD_23        =   23, // reserved
    XSDMA_DRCMR_ID_USB_UDC_EP_0   =   24, // USB endpoint 0 request
    XSDMA_DRCMR_ID_USB_UDC_EP_A   =   25, // USB endpoint A request
    XSDMA_DRCMR_ID_USB_UDC_EP_B   =   26, // USB endpoint B request
    XSDMA_DRCMR_ID_USB_UDC_EP_C   =   27, // USB endpoint C request
    XSDMA_DRCMR_ID_USB_UDC_EP_D   =   28, // USB endpoint D request
    XSDMA_DRCMR_ID_USB_UDC_EP_E   =   29, // USB endpoint E request
    XSDMA_DRCMR_ID_USB_UDC_EP_F   =   30, // USB endpoint F request
    XSDMA_DRCMR_ID_USB_UDC_EP_G   =   31, // USB endpoint G request
    XSDMA_DRCMR_ID_USB_UDC_EP_H   =   32, // USB endpoint H request
    XSDMA_DRCMR_ID_USB_UDC_EP_I   =   33, // USB endpoint I request
    XSDMA_DRCMR_ID_USB_UDC_EP_J   =   34, // USB endpoint J request
    XSDMA_DRCMR_ID_USB_UDC_EP_K   =   35, // USB endpoint K request
    XSDMA_DRCMR_ID_USB_UDC_EP_L   =   36, // USB endpoint L request
    XSDMA_DRCMR_ID_USB_UDC_EP_M   =   37, // USB endpoint M request
    XSDMA_DRCMR_ID_USB_UDC_EP_N   =   38, // USB endpoint N request
    XSDMA_DRCMR_ID_USB_UDC_EP_P   =   39, // USB endpoint P request
    XSDMA_DRCMR_ID_USB_UDC_EP_Q   =   40, // USB endpoint Q request
    XSDMA_DRCMR_ID_USB_UDC_EP_R   =   41, // USB endpoint R request
    XSDMA_DRCMR_ID_USB_UDC_EP_S   =   42, // USB endpoint S request
    XSDMA_DRCMR_ID_USB_UDC_EP_T   =   43, // USB endpoint T request
    XSDMA_DRCMR_ID_USB_UDC_EP_U   =   44, // USB endpoint U request
    XSDMA_DRCMR_ID_USB_UDC_EP_V   =   45, // USB endpoint V request
    XSDMA_DRCMR_ID_USB_UDC_EP_W   =   46, // USB endpoint W request
    XSDMA_DRCMR_ID_USB_UDC_EP_X   =   47, // USB endpoint X request
    XSDMA_DRCMR_ID_BASEBAND_RX_1  =   48, // Baseband Receive Request 1
    XSDMA_DRCMR_ID_BASEBAND_TX_1  =   49, // Baseband Transmit Request 1
    XSDMA_DRCMR_ID_BASEBAND_RX_2  =   50, // Baseband Receive Request 2
    XSDMA_DRCMR_ID_BASEBAND_TX_2  =   51, // Baseband Transmit Request 2
    XSDMA_DRCMR_ID_BASEBAND_RX_3  =   52, // Baseband Receive Request 3
    XSDMA_DRCMR_ID_BASEBAND_TX_3  =   53, // Baseband Transmit Request 3
    XSDMA_DRCMR_ID_BASEBAND_RX_4  =   54, // Baseband Receive Request 4
    XSDMA_DRCMR_ID_BASEBAND_TX_4  =   55, // Baseband Transmit Request 4
    XSDMA_DRCMR_ID_BASEBAND_RX_5  =   56, // Baseband Receive Request 5
    XSDMA_DRCMR_ID_BASEBAND_TX_5  =   57, // Baseband Transmit Request 5
    XSDMA_DRCMR_ID_BASEBAND_RX_6  =   58, // Baseband Receive Request 6
    XSDMA_DRCMR_ID_BASEBAND_TX_6  =   59, // Baseband Transmit Request 6
    XSDMA_DRCMR_ID_BASEBAND_RX_7  =   60, // Baseband Receive Request 7
    XSDMA_DRCMR_ID_BASEBAND_TX_7  =   61, // Baseband Transmit Request 7
    XSDMA_DRCMR_ID_USIM_RX        =   62, // USIM receive request
    XSDMA_DRCMR_ID_USIM_TX        =   63, // USIM transmit request
    XSDMA_DRCMR2_ID_MEM_STICK_RX  = 1024, // Memory Stick receive request
    XSDMA_DRCMR2_ID_MEM_STICK_TX  = 1025, // Memory Stick transmit request
    XSDMA_DRCMR2_ID_SSP3_RX       = 1026, // SSP3 receive request
    XSDMA_DRCMR2_ID_SSP3_TX       = 1027, // SSP3 transmit request
    
    XSDMA_DRCMR_ID_MAX            = XSDMA_DRCMR_ID_USIM_TX,
    XSDMA_DRCMR_ID_NUM            = (XSDMA_DRCMR_ID_MAX+1),
    XSDMA_DRCMR_ID_ILLEGAL        = XSDMA_DRCMR_ID_NUM,

    XSDMA_DRCMR2_ID_NUM           = (XSDMA_DRCMR2_ID_SSP3_TX - XSDMA_DRCMR2_ID_MEM_STICK_RX) + 1,
    
    // Memory doesn't have a DRCMR.  Define this for users of records
    //  where XsDmaDrcmrIdT values are stored.
    XSDMA_DRCMR_ID_MEMORY         = (XSDMA_DRCMR_ID_NUM+1)

} XsDmaDrcmrIdT;

/*
*******************************************************************************
Mask version of the DMA control register set structure
*******************************************************************************
*/

typedef struct XsDmaCtrlS {
    VUINT32   DCSR[XSDMA_CHANNEL_NUM]; //DMA CSRs by channel

    UINT32    PAD0[28];  // unused addresses
    VUINT32   DINT;        // DMA interrupt register

    UINT32    PAD1[3];  // unused addresses                           // Indexed by the XsDmaDrcmrIdT enums.
    VUINT32   DRCMR[XSDMA_DRCMR_ID_NUM];
    XsDmaDescriptorGroupT DDG[XSDMA_CHANNEL_NUM]; // DMA descriptor group array
    UINT32    PAD2[832];
    VUINT32   DRCMR2[XSDMA_DRCMR2_ID_NUM];

} XsDmaCtrlT;

/*
*******************************************************************************
This structure is used to pass a bucket of parameters around when creating 
DMA descriptors.  Descriptors can be for memory to memory transfers,
peripheral to memory, or mem to peripheral.
*******************************************************************************
*/

typedef struct XsDmaDescriptorParamsS
{
    // Information to create and determine the properties of the descriptor
    XsDmaDescriptorElementsTPT thisDescP;
    INT channel;
    INT transferLength;
    BOOL setStopBit;

    // Contents of the descriptor to be built
    UINT32 nextPhysicalAddr;
    UINT32 sourcePhysicalAddr;
    UINT32 targetPhysicalAddr;
    UINT32 commandRegister;
    XsDmaDescriptorElementsTPT nextVirtualAddr;
    PVOID  sourceVirtualAddr;
    PVOID  targetVirtualAddr;
    UINT32 sourceDeviceType;
    UINT32 targetDeviceType;
    UINT32 currentPhysicalAddr; // the physical address of this descriptor
    XsDmaDescriptorElementsTPT prevDescrP;

} XsDmaDescriptorParamsT;

/*
*******************************************************************************
    Constants and structure for main processor DMA Controller's channel 
    configuration table.  Includes members for the registered client interrupt 
    handlers (callbacks).
*******************************************************************************
*/

typedef struct XsDmaChannelConfigEntryS
{
    BOOL        isAssigned;            // Channel has been assigned
    XsDmaDeviceNamesT
                sourceDeviceName;
    XsDmaDeviceNamesT
                targetDeviceName;
    XsDmaDrcmrIdT
                drcmrId;
    XsDmaHandlerFnPT                   // Pointer to the client's registered 
                registeredHandlerFnP;  //  handler for this channel.
    void*       registeredParamP;      // Pass back to registered handler

} XsDmaChannelConfigEntryT;


static
XsDmaChannelConfigEntryT XsDmaChannelConfigTable [XSDMA_CHANNEL_NUM];

/*
*******************************************************************************
    Function prototypes
*******************************************************************************
*/

static void XsDmaInitAll(void);
static INT  XsDmaModifyChannelUsage(ChannelOperationsT, 
                                      INT32, 
                                      XsDmaChannelPriorityT, 
                                      XsDmaChannelStatusT*);
static void XsDmaSetupMem2MemDescriptor (XsDmaDescriptorParamsT* );
static void XsDmaSetupMem2PeriphDescriptor(XsDmaDescriptorParamsT* );
static void XsDmaSetupPeriph2MemDescriptor(XsDmaDescriptorParamsT* );
static void XsDmaInterruptHandler (void *);
static XsDmaDrcmrIdT XsDmaMapDevice2DrcmrId (XsDmaDeviceNamesT, BOOL);
static void XsDmaFillDescriptorStructure (XsDmaDescriptorParamsT*);
static UINT32 XsDmaDestroyLink (XsDmaDescriptorElementsTPT);
static UINT32 XsDmaPopulateDescWithBufs (XsDmaDescriptorElementsTPT );


/********************************************************************************/

#endif // C_DMA_CONTROLLER