#include "BasicDefinition.h"

/*******************************************************************************/
/*       the follow function init emif interface to a sdram(4M*16bit)		   */
/*       the procedure of configuration sdram is shown as below                */
/*  1) Clear the MEMCEN bit in the EMIF global control register (EGCR). This   */
/*     prevents the memory clock from being driven on the CLKMEM pin.          */
/*  2) Keeping MEMCEN = 0, program the other programmable fields of EGCR:      */
/*     MEMFREQ, WPE, NOHOLD, and (if asynchronous memory is used in any        */
/*     of the CE spaces) ARDYOFF.                                              */
/*  3) For each CE space that contains SDRAM, set MTYPE = 011b in CE space     */
/*     control register 1.                                                     */
/*  4) Program SDRAM control register 1.                                       */
/*  5) Program SDRAM control register 2.                                       */
/*  6) If the EMIF is responsible for refreshing the SDRAM, write the desired  */
/*     refresh period to the SDRAM period register.                            */
/*  7) Set the MEMCEN bit in EGCR, so that the memory clock is driven on the   */
/*     CLKMEM pin.                                                             */
/*  8) Write to the SDRAM initialization register. After new values are written*/ 
/*     to EMIF configuration registers, 6 CPU clock cycles are required for the*/ 
/*     new configuration to propagate through the EMIF logic. After this delay,*/
/*     the EMIF begins the SDRAM initialization sequence.                      */
/*******************************************************************************/
void delay(UINT Xms)//12MHz
{
	UINT i,j;
	
	for(i=0;i<Xms;i++)
	{
		for(j=0;j<1000;j++)
			asm(" nop ");
	}
}



void emif_init()
{
	EBSR = 0x0201;
	//reset emif
	EMIF_GRST = 0xFFFF;
	//disable MEMCEN
	EMIF_GCTRL=0x0000;
	//keep memcen=0, let MEMFPEQ=01b(sdramclk=1/2dspclk),WPE=0,NOHOLD=1 DISABLED 
	//EMIF_GCTRL=EMIF_GCTRL|0x0001;
	//MTYPE=011b sdram, others remain default values
	EMIF_CE2_CTRL1=0x3FFF;
	//remain default values
	EMIF_CE2_CTRL2=0x5FFF;
	//remain default values
	EMIF_CE2_CTRL3=0x0000;
	EMIF_CE0_CTRL3=0x0000;
	EMIF_CE1_CTRL3=0x0000;
	EMIF_CE3_CTRL1=0x3FFF;
	EMIF_CE3_CTRL3=0x0000;
	/*SDRAM使用了MT48LC2M32B2-7   Tcyc=2*5510's clock period=10ns=CLKMEM's period.
   TRC=tRC/Tcyc - 1= 70/10 - 1=6
   TRP=tRP/Tcyc -1= 20/10 -1= 1 要取比所得的數(shù)大的最小整數(shù)
   TRCD= (tRCD/Tcyc) - 1 =20/10 -1=1
   Tmrd=(tMRD/Tcyc) - 1= 2/10 -1=1
   Tras=(tRAS/Tcyc) - 1= 42/10 -1=4
   Tactv2actv= (tRRD/Tcyc) - 1 = 14/10 - 1 = 1
   RFEN=1   REFRESH ENABLE
   SDWID=0  SDRAM WIDTH= 16BIT
   SDSIZE=0  SDRAM SIZE= 4M*32BIT=64MBIT
   SDACC =0  SDRAM data bus interface is 16 bits wide .   
   PERIOD=0x8B8  PERIOD = Trefresh/Tcyc  tRefresh = 64 ms / 4096 = 15.625us 
   Period = 1562cycles = 0x61A cycles */
	EMIF_SDRAM_CTRL1=0x3111;//0xF1FF;//0x2b01;
	EMIF_SDRAM_CTRL2=0x0141;//0x0535
	EMIF_SDRAM_PER=0x061A;//0x0578;
	EMIF_SDRAM_CNTR=0x0000;
	EMIF_SDRAM_INIT=0x0FFF; 
	delay(100);
	//don't forget to enable the clock to the memory
	EMIF_GCTRL=EMIF_GCTRL|0x0020;
}