; half duplex UART code by Rich Ottosen

        cblock
bitcnt
dlycnt
serreg
        endc


speed	equ	26-3		; 9600 bps


;transmit character in w as 8 bits, no parity, 1 stop
;  this routine has the start, stop and data bits inverted because an inverting
;  rs-232 buffer is not used.

xmit:	movwf	serreg
	movlw	10		;put # of data bits + start bit + # stop bits
	movwf	bitcnt		; into counter
        bsf     STATUS,C        ;set up the stop bit
        bsf     txd             ;send start bit

xmt10:	movlw	speed		;delay 1 bit time
	movwf	dlycnt
xd1:	nop			;				1 cycle
	decfsz	dlycnt		;				1
	goto	xd1		;				2 =4 cycles

	decf	bitcnt		;count the data bits
        btfsc   STATUS,Z
	goto	xmt30		; and exit when done
	rrf	serreg		;get data bit into carry
        btfsc   STATUS,C        ;if carry is set
        bcf     txd             ; then xmit a zero
        btfss   STATUS,C        ;if carry is clear
        bsf     txd             ; then transmit a one
	goto	xmt10

xmt30:	retlw	0		;return nothing


;receive a character as 8 bits, no parity, 1 stop and put in "serreg" and W
;  this routine has the start, stop and data bits inverted because an inverting
;  rs-232 buffer is not used.

recv:	movlw	9		;put # of data bits + 1 stop
	movwf	bitcnt		; into counter
rc05:	btfss	rxd		;wait for the start bit
	goto	rc05

rdly1:	movlw	speed		;delay 1/2 bit time
	movwf	dlycnt
        bcf     STATUS,C        ; by dividing "speed" by 2
	rrf	dlycnt
rd1:	nop			;				1 cycle
	decfsz	dlycnt		;				1
	goto	rd1		;				2 =4 cycles

	btfss	rxd		;is start still active?
	goto	recv		; try again if not

rc10:	movlw	speed		;delay 1 bit time
	movwf	dlycnt
rd2:	nop			;				1 cycle
	decfsz	dlycnt		;				1
	goto	rd2		;				2 =4 cycles

	decf	bitcnt		;count the data bits
        btfsc   STATUS,Z
	goto	rc40		; and exit when done

	btfss	rxd		;if data is a zero
        bsf     STATUS,C        ; then set the carry
	btfsc	rxd		;if data is a one
        bcf     STATUS,C        ; then clear the carry
	rrf	serreg		;get carry into data bit 
	goto	rc10

rc40:   movf    serreg,W
	return