?? de2_default.fit.talkback.xml
字號:
<pci_i_o_enabled>no</pci_i_o_enabled>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
</row>
<row>
<name>SW[7]</name>
<pin__>C13</pin__>
<i_o_bank>3</i_o_bank>
<x_coordinate>31</x_coordinate>
<y_coordinate>36</y_coordinate>
<cell_number>2</cell_number>
<combinational_fan_out>0</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>no</global>
<input_register>no</input_register>
<power_up_high>no</power_up_high>
<pci_i_o_enabled>no</pci_i_o_enabled>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
</row>
<row>
<name>SW[8]</name>
<pin__>B13</pin__>
<i_o_bank>4</i_o_bank>
<x_coordinate>31</x_coordinate>
<y_coordinate>36</y_coordinate>
<cell_number>0</cell_number>
<combinational_fan_out>0</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>no</global>
<input_register>no</input_register>
<power_up_high>no</power_up_high>
<pci_i_o_enabled>no</pci_i_o_enabled>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
</row>
<row>
<name>SW[9]</name>
<pin__>A13</pin__>
<i_o_bank>4</i_o_bank>
<x_coordinate>31</x_coordinate>
<y_coordinate>36</y_coordinate>
<cell_number>1</cell_number>
<combinational_fan_out>0</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>no</global>
<input_register>no</input_register>
<power_up_high>no</power_up_high>
<pci_i_o_enabled>no</pci_i_o_enabled>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
</row>
<row>
<name>TCK</name>
<pin__>D14</pin__>
<i_o_bank>4</i_o_bank>
<x_coordinate>33</x_coordinate>
<y_coordinate>36</y_coordinate>
<cell_number>0</cell_number>
<combinational_fan_out>0</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>no</global>
<input_register>no</input_register>
<power_up_high>no</power_up_high>
<pci_i_o_enabled>no</pci_i_o_enabled>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
</row>
<row>
<name>TCS</name>
<pin__>A14</pin__>
<i_o_bank>4</i_o_bank>
<x_coordinate>33</x_coordinate>
<y_coordinate>36</y_coordinate>
<cell_number>1</cell_number>
<combinational_fan_out>0</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>no</global>
<input_register>no</input_register>
<power_up_high>no</power_up_high>
<pci_i_o_enabled>no</pci_i_o_enabled>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
</row>
<row>
<name>TDI</name>
<pin__>B14</pin__>
<i_o_bank>4</i_o_bank>
<x_coordinate>33</x_coordinate>
<y_coordinate>36</y_coordinate>
<cell_number>2</cell_number>
<combinational_fan_out>0</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>no</global>
<input_register>no</input_register>
<power_up_high>no</power_up_high>
<pci_i_o_enabled>no</pci_i_o_enabled>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
</row>
<row>
<name>TD_DATA[0]</name>
<pin__>J9</pin__>
<i_o_bank>3</i_o_bank>
<x_coordinate>5</x_coordinate>
<y_coordinate>36</y_coordinate>
<cell_number>0</cell_number>
<combinational_fan_out>0</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>no</global>
<input_register>no</input_register>
<power_up_high>no</power_up_high>
<pci_i_o_enabled>no</pci_i_o_enabled>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
</row>
<row>
<name>TD_DATA[1]</name>
<pin__>E8</pin__>
<i_o_bank>3</i_o_bank>
<x_coordinate>7</x_coordinate>
<y_coordinate>36</y_coordinate>
<cell_number>3</cell_number>
<combinational_fan_out>0</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>no</global>
<input_register>no</input_register>
<power_up_high>no</power_up_high>
<pci_i_o_enabled>no</pci_i_o_enabled>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
</row>
<row>
<name>TD_DATA[2]</name>
<pin__>H8</pin__>
<i_o_bank>3</i_o_bank>
<x_coordinate>7</x_coordinate>
<y_coordinate>36</y_coordinate>
<cell_number>2</cell_number>
<combinational_fan_out>0</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>no</global>
<input_register>no</input_register>
<power_up_high>no</power_up_high>
<pci_i_o_enabled>no</pci_i_o_enabled>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
</row>
<row>
<name>TD_DATA[3]</name>
<pin__>H10</pin__>
<i_o_bank>3</i_o_bank>
<x_coordinate>7</x_coordinate>
<y_coordinate>36</y_coordinate>
<cell_number>1</cell_number>
<combinational_fan_out>0</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>no</global>
<input_register>no</input_register>
<power_up_high>no</power_up_high>
<pci_i_o_enabled>no</pci_i_o_enabled>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
</row>
<row>
<name>TD_DATA[4]</name>
<pin__>G9</pin__>
<i_o_bank>3</i_o_bank>
<x_coordinate>7</x_coordinate>
<y_coordinate>36</y_coordinate>
<cell_number>0</cell_number>
<combinational_fan_out>0</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>no</global>
<input_register>no</input_register>
<power_up_high>no</power_up_high>
<pci_i_o_enabled>no</pci_i_o_enabled>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
</row>
<row>
<name>TD_DATA[5]</name>
<pin__>F9</pin__>
<i_o_bank>3</i_o_bank>
<x_coordinate>9</x_coordinate>
<y_coordinate>36</y_coordinate>
<cell_number>2</cell_number>
<combinational_fan_out>0</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>no</global>
<input_register>no</input_register>
<power_up_high>no</power_up_high>
<pci_i_o_enabled>no</pci_i_o_enabled>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
</row>
<row>
<name>TD_DATA[6]</name>
<pin__>D7</pin__>
<i_o_bank>3</i_o_bank>
<x_coordinate>9</x_coordinate>
<y_coordinate>36</y_coordinate>
<cell_number>1</cell_number>
<combinational_fan_out>0</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>no</global>
<input_register>no</input_register>
<power_up_high>no</power_up_high>
<pci_i_o_enabled>no</pci_i_o_enabled>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
</row>
<row>
<name>TD_DATA[7]</name>
<pin__>C7</pin__>
<i_o_bank>3</i_o_bank>
<x_coordinate>9</x_coordinate>
<y_coordinate>36</y_coordinate>
<cell_number>0</cell_number>
<combinational_fan_out>0</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>no</global>
<input_register>no</input_register>
<power_up_high>no</power_up_high>
<pci_i_o_enabled>no</pci_i_o_enabled>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
</row>
<row>
<name>TD_HS</name>
<pin__>D5</pin__>
<i_o_bank>3</i_o_bank>
<x_coordinate>5</x_coordinate>
<y_coordinate>36</y_coordinate>
<cell_number>2</cell_number>
<combinational_fan_out>0</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>no</global>
<input_register>no</input_register>
<power_up_high>no</power_up_high>
<pci_i_o_enabled>no</pci_i_o_enabled>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
</row>
<row>
<name>TD_VS</name>
<pin__>K9</pin__>
<i_o_bank>3</i_o_bank>
<x_coordinate>5</x_coordinate>
<y_coordinate>36</y_coordinate>
<cell_number>1</cell_number>
<combinational_fan_out>0</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>no</global>
<input_register>no</input_register>
<power_up_high>no</power_up_high>
<pci_i_o_enabled>no</pci_i_o_enabled>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
</row>
<row>
<name>UART_RXD</name>
<pin__>C25</pin__>
<i_o_bank>5</i_o_bank>
<x_coordinate>65</x_coordinate>
<y_coordinate>32</y_coordinate>
<cell_number>2</cell_number>
<combinational_fan_out>0</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>no</global>
<input_register>no</input_register>
<power_up_high>no</power_up_high>
<pci_i_o_enabled>no</pci_i_o_enabled>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
</row>
</input_pins>
<output_pins>
<row>
<name>AUD_ADCLRCK</name>
<pin__>C5</pin__>
<i_o_bank>3</i_o_bank>
<x_coordinate>1</x_coordinate>
<y_coordinate>36</y_coordinate>
<cell_number>3</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
<load units="pF">0</load>
</row>
<row>
<name>AUD_BCLK</name>
<pin__>B4</pin__>
<i_o_bank>3</i_o_bank>
<x_coordinate>1</x_coordinate>
<y_coordinate>36</y_coordinate>
<cell_number>0</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
<load units="pF">0</load>
</row>
<row>
<name>AUD_DACDAT</name>
<pin__>A4</pin__>
<i_o_bank>3</i_o_bank>
<x_coordinate>1</x_coordinate>
<y_coordinate>36</y_coordinate>
<cell_number>1</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
<load units="pF">0</load>
</row>
<row>
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