?? de2_default.map.talkback.xml
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<!--
This XML file (created on Mon Oct 01 08:36:38 2007) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature. To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder. For more information, go
to www.altera.com/products/software/download/dnl-download_license.html
-->
<talkback>
<ver>6.0</ver>
<schema>quartus_version_6.0_build_202.xsd</schema>
<license>
<host_id>00123f4b0b3f</host_id>
<nic_id>00123f4b0b3f</nic_id>
<cdrive_id>882dfa9e</cdrive_id>
</license>
<tool>
<name>Quartus II</name>
<version>6.0</version>
<build>Build 202</build>
<service_pack_label>1</service_pack_label>
<binary_type>32</binary_type>
<module>quartus_map</module>
<edition>Web Edition</edition>
<eval>Licensed</eval>
<compilation_end_time>Mon Oct 01 08:36:38 2007</compilation_end_time>
</tool>
<machine>
<os>Windows XP</os>
<cpu>
<proc_count>2</proc_count>
<cpu_freq units="MHz">3391</cpu_freq>
</cpu>
<ram units="MB">1023</ram>
</machine>
<project>C:/DE2/NoiseCancel/DE2_Default</project>
<revision>DE2_Default</revision>
<compilation_summary>
<flow_status>Successful - Mon Oct 01 08:36:37 2007</flow_status>
<quartus_ii_version>6.0 Build 202 06/20/2006 SP 1 SJ Web Edition</quartus_ii_version>
<revision_name>DE2_Default</revision_name>
<top_level_entity_name>DE2_Default</top_level_entity_name>
<family>Cyclone II</family>
<device>EP2C35F672C6</device>
<timing_models>Final</timing_models>
<met_timing_requirements>N/A</met_timing_requirements>
<total_logic_elements>607</total_logic_elements>
<total_registers>491</total_registers>
<total_pins>429</total_pins>
<total_virtual_pins>0</total_virtual_pins>
<total_memory_bits>4,608</total_memory_bits>
<embedded_multiplier_9_bit_elements>4</embedded_multiplier_9_bit_elements>
<total_plls>1</total_plls>
</compilation_summary>
<lpm_params>
<lpm_data type="lpm_mult" num_inst="2">
<inst name="signed_mult:w2xRefShifted|lpm_mult:Mult0">
<param name="LPM_WIDTHA" value="18"></param>
<param name="LPM_WIDTHB" value="18"></param>
<param name="LPM_WIDTHP" value="36"></param>
<param name="LPM_REPRESENTATION" value="SIGNED"></param>
<param name="INPUT_A_IS_CONSTANT" value="NO"></param>
<param name="INPUT_B_IS_CONSTANT" value="NO"></param>
<param name="USE_EAB" value="OFF"></param>
<param name="DEDICATED_MULTIPLIER_CIRCUITRY" value="AUTO"></param>
<param name="INPUT_A_FIXED_VALUE" value="Bx"></param>
<param name="INPUT_B_FIXED_VALUE" value="Bx"></param>
</inst>
<inst name="signed_mult:w1xRef|lpm_mult:Mult0">
<param name="LPM_WIDTHA" value="18"></param>
<param name="LPM_WIDTHB" value="18"></param>
<param name="LPM_WIDTHP" value="36"></param>
<param name="LPM_REPRESENTATION" value="SIGNED"></param>
<param name="INPUT_A_IS_CONSTANT" value="NO"></param>
<param name="INPUT_B_IS_CONSTANT" value="NO"></param>
<param name="USE_EAB" value="OFF"></param>
<param name="DEDICATED_MULTIPLIER_CIRCUITRY" value="AUTO"></param>
<param name="INPUT_A_FIXED_VALUE" value="Bx"></param>
<param name="INPUT_B_FIXED_VALUE" value="Bx"></param>
</inst>
</lpm_data>
</lpm_params>
<dsp_block_usage_summary>
<row>
<statistic>Simple Multipliers (9-bit)</statistic>
<number_used>0</number_used>
</row>
<row>
<statistic>Simple Multipliers (18-bit)</statistic>
<number_used>2</number_used>
</row>
<row>
<statistic>Embedded Multiplier Blocks</statistic>
</row>
<row>
<statistic>Embedded Multiplier 9-bit elements</statistic>
<number_used>4</number_used>
</row>
<row>
<statistic>Signed Embedded Multipliers</statistic>
<number_used>2</number_used>
</row>
<row>
<statistic>Unsigned Embedded Multipliers</statistic>
<number_used>0</number_used>
</row>
<row>
<statistic>Mixed Sign Embedded Multipliers</statistic>
<number_used>0</number_used>
</row>
<row>
<statistic>Variable Sign Embedded Multipliers</statistic>
<number_used>0</number_used>
</row>
<row>
<statistic>Dedicated Input Shift Register Chains</statistic>
<number_used>0</number_used>
</row>
</dsp_block_usage_summary>
<mep_data>
<command_line>quartus_map --read_settings_files=on --write_settings_files=off DE2_Default -c DE2_Default</command_line>
</mep_data>
<software_data>
<smart_recompile>off</smart_recompile>
</software_data>
<messages>
<warning>Warning: Design contains 41 input pin(s) that do not drive logic</warning>
<warning>Warning: No output dependent on input pin "TD_VS"</warning>
<warning>Warning: No output dependent on input pin "TD_HS"</warning>
<warning>Warning: No output dependent on input pin "TD_DATA[7]"</warning>
<warning>Warning: No output dependent on input pin "TD_DATA[6]"</warning>
<info>Info: Quartus II Analysis & Synthesis was successful. 0 errors, 488 warnings</info>
<info>Info: Elapsed time: 00:00:22</info>
<info>Info: Processing ended: Mon Oct 01 08:36:37 2007</info>
<info>Info: Implemented 1210 device resources after synthesis - the final resource count might be different</info>
<info>Info: Implemented 4 DSP elements</info>
</messages>
<analysis___synthesis_settings>
<row>
<option>Device</option>
<setting>EP2C35F672C6</setting>
</row>
<row>
<option>Top-level entity name</option>
<setting>DE2_Default</setting>
<default_value>DE2_Default</default_value>
</row>
<row>
<option>Family name</option>
<setting>Cyclone II</setting>
<default_value>Stratix</default_value>
</row>
<row>
<option>Use smart compilation</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Restructure Multiplexers</option>
<setting>Auto</setting>
<default_value>Auto</default_value>
</row>
<row>
<option>Create Debugging Nodes for IP Cores</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Preserve fewer node names</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Disable OpenCore Plus hardware evaluation</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Verilog Version</option>
<setting>Verilog_2001</setting>
<default_value>Verilog_2001</default_value>
</row>
<row>
<option>VHDL Version</option>
<setting>VHDL93</setting>
<default_value>VHDL93</default_value>
</row>
<row>
<option>State Machine Processing</option>
<setting>Auto</setting>
<default_value>Auto</default_value>
</row>
<row>
<option>Extract Verilog State Machines</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Extract VHDL State Machines</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Add Pass-Through Logic to Inferred RAMs</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>DSP Block Balancing</option>
<setting>Auto</setting>
<default_value>Auto</default_value>
</row>
<row>
<option>Maximum DSP Block Usage</option>
<setting>Unlimited</setting>
<default_value>Unlimited</default_value>
</row>
<row>
<option>NOT Gate Push-Back</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Power-Up Don't Care</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Remove Redundant Logic Cells</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Remove Duplicate Registers</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Ignore CARRY Buffers</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore CASCADE Buffers</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore GLOBAL Buffers</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore ROW GLOBAL Buffers</option>
<setting>Off</setting>
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