?? altsyncram_jri2.tdf
字號(hào):
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 7,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 26,
PORT_A_LAST_ADDRESS = 127,
PORT_A_LOGICAL_RAM_DEPTH = 128,
PORT_A_LOGICAL_RAM_WIDTH = 38,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 7,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 26,
PORT_B_LAST_ADDRESS = 127,
PORT_B_LOGICAL_RAM_DEPTH = 128,
PORT_B_LOGICAL_RAM_WIDTH = 38,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a27 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 7,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 27,
PORT_A_LAST_ADDRESS = 127,
PORT_A_LOGICAL_RAM_DEPTH = 128,
PORT_A_LOGICAL_RAM_WIDTH = 38,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 7,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 27,
PORT_B_LAST_ADDRESS = 127,
PORT_B_LOGICAL_RAM_DEPTH = 128,
PORT_B_LOGICAL_RAM_WIDTH = 38,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a28 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 7,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 28,
PORT_A_LAST_ADDRESS = 127,
PORT_A_LOGICAL_RAM_DEPTH = 128,
PORT_A_LOGICAL_RAM_WIDTH = 38,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 7,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 28,
PORT_B_LAST_ADDRESS = 127,
PORT_B_LOGICAL_RAM_DEPTH = 128,
PORT_B_LOGICAL_RAM_WIDTH = 38,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a29 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 7,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 29,
PORT_A_LAST_ADDRESS = 127,
PORT_A_LOGICAL_RAM_DEPTH = 128,
PORT_A_LOGICAL_RAM_WIDTH = 38,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 7,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 29,
PORT_B_LAST_ADDRESS = 127,
PORT_B_LOGICAL_RAM_DEPTH = 128,
PORT_B_LOGICAL_RAM_WIDTH = 38,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a30 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 7,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 30,
PORT_A_LAST_ADDRESS = 127,
PORT_A_LOGICAL_RAM_DEPTH = 128,
PORT_A_LOGICAL_RAM_WIDTH = 38,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 7,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 30,
PORT_B_LAST_ADDRESS = 127,
PORT_B_LOGICAL_RAM_DEPTH = 128,
PORT_B_LOGICAL_RAM_WIDTH = 38,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a31 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 7,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 31,
PORT_A_LAST_ADDRESS = 127,
PORT_A_LOGICAL_RAM_DEPTH = 128,
PORT_A_LOGICAL_RAM_WIDTH = 38,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 7,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 31,
PORT_B_LAST_ADDRESS = 127,
PORT_B_LOGICAL_RAM_DEPTH = 128,
PORT_B_LOGICAL_RAM_WIDTH = 38,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a32 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 7,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 32,
PORT_A_LAST_ADDRESS = 127,
PORT_A_LOGICAL_RAM_DEPTH = 128,
PORT_A_LOGICAL_RAM_WIDTH = 38,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 7,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 32,
PORT_B_LAST_ADDRESS = 127,
PORT_B_LOGICAL_RAM_DEPTH = 128,
PORT_B_LOGICAL_RAM_WIDTH = 38,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a33 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 7,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 33,
PORT_A_LAST_ADDRESS = 127,
PORT_A_LOGICAL_RAM_DEPTH = 128,
PORT_A_LOGICAL_RAM_WIDTH = 38,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 7,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 33,
PORT_B_LAST_ADDRESS = 127,
PORT_B_LOGICAL_RAM_DEPTH = 128,
PORT_B_LOGICAL_RAM_WIDTH = 38,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a34 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 7,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 34,
PORT_A_LAST_ADDRESS = 127,
PORT_A_LOGICAL_RAM_DEPTH = 128,
PORT_A_LOGICAL_RAM_WIDTH = 38,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 7,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 34,
PORT_B_LAST_ADDRESS = 127,
PORT_B_LOGICAL_RAM_DEPTH = 128,
PORT_B_LOGICAL_RAM_WIDTH = 38,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a35 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 7,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 35,
PORT_A_LAST_ADDRESS = 127,
PORT_A_LOGICAL_RAM_DEPTH = 128,
PORT_A_LOGICAL_RAM_WIDTH = 38,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 7,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 35,
PORT_B_LAST_ADDRESS = 127,
PORT_B_LOGICAL_RAM_DEPTH = 128,
PORT_B_LOGICAL_RAM_WIDTH = 38,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a36 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 7,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 36,
PORT_A_LAST_ADDRESS = 127,
PORT_A_LOGICAL_RAM_DEPTH = 128,
PORT_A_LOGICAL_RAM_WIDTH = 38,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 7,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 36,
PORT_B_LAST_ADDRESS = 127,
PORT_B_LOGICAL_RAM_DEPTH = 128,
PORT_B_LOGICAL_RAM_WIDTH = 38,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a37 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 7,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 37,
PORT_A_LAST_ADDRESS = 127,
PORT_A_LOGICAL_RAM_DEPTH = 128,
PORT_A_LOGICAL_RAM_WIDTH = 38,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 7,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 37,
PORT_B_LAST_ADDRESS = 127,
PORT_B_LOGICAL_RAM_DEPTH = 128,
PORT_B_LOGICAL_RAM_WIDTH = 38,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
address_a_wire[6..0] : WIRE;
address_b_wire[6..0] : WIRE;
BEGIN
ram_block1a[37..0].clk0 = clock0;
ram_block1a[37..0].clk1 = clock1;
ram_block1a[37..0].ena0 = wren_a;
ram_block1a[37..0].ena1 = clocken1;
ram_block1a[37..0].portaaddr[] = ( address_a_wire[6..0]);
ram_block1a[0].portadatain[] = ( data_a[0..0]);
ram_block1a[1].portadatain[] = ( data_a[1..1]);
ram_block1a[2].portadatain[] = ( data_a[2..2]);
ram_block1a[3].portadatain[] = ( data_a[3..3]);
ram_block1a[4].portadatain[] = ( data_a[4..4]);
ram_block1a[5].portadatain[] = ( data_a[5..5]);
ram_block1a[6].portadatain[] = ( data_a[6..6]);
ram_block1a[7].portadatain[] = ( data_a[7..7]);
ram_block1a[8].portadatain[] = ( data_a[8..8]);
ram_block1a[9].portadatain[] = ( data_a[9..9]);
ram_block1a[10].portadatain[] = ( data_a[10..10]);
ram_block1a[11].portadatain[] = ( data_a[11..11]);
ram_block1a[12].portadatain[] = ( data_a[12..12]);
ram_block1a[13].portadatain[] = ( data_a[13..13]);
ram_block1a[14].portadatain[] = ( data_a[14..14]);
ram_block1a[15].portadatain[] = ( data_a[15..15]);
ram_block1a[16].portadatain[] = ( data_a[16..16]);
ram_block1a[17].portadatain[] = ( data_a[17..17]);
ram_block1a[18].portadatain[] = ( data_a[18..18]);
ram_block1a[19].portadatain[] = ( data_a[19..19]);
ram_block1a[20].portadatain[] = ( data_a[20..20]);
ram_block1a[21].portadatain[] = ( data_a[21..21]);
ram_block1a[22].portadatain[] = ( data_a[22..22]);
ram_block1a[23].portadatain[] = ( data_a[23..23]);
ram_block1a[24].portadatain[] = ( data_a[24..24]);
ram_block1a[25].portadatain[] = ( data_a[25..25]);
ram_block1a[26].portadatain[] = ( data_a[26..26]);
ram_block1a[27].portadatain[] = ( data_a[27..27]);
ram_block1a[28].portadatain[] = ( data_a[28..28]);
ram_block1a[29].portadatain[] = ( data_a[29..29]);
ram_block1a[30].portadatain[] = ( data_a[30..30]);
ram_block1a[31].portadatain[] = ( data_a[31..31]);
ram_block1a[32].portadatain[] = ( data_a[32..32]);
ram_block1a[33].portadatain[] = ( data_a[33..33]);
ram_block1a[34].portadatain[] = ( data_a[34..34]);
ram_block1a[35].portadatain[] = ( data_a[35..35]);
ram_block1a[36].portadatain[] = ( data_a[36..36]);
ram_block1a[37].portadatain[] = ( data_a[37..37]);
ram_block1a[37..0].portawe = B"11111111111111111111111111111111111111";
ram_block1a[37..0].portbaddr[] = ( address_b_wire[6..0]);
ram_block1a[37..0].portbrewe = B"11111111111111111111111111111111111111";
address_a_wire[] = address_a[];
address_b_wire[] = address_b[];
q_b[] = ( ram_block1a[37..0].portbdataout[0..0]);
END;
--VALID FILE
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