{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Web Edition " "Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Oct 01 08:36:46 2007 " "Info: Processing started: Mon Oct 01 08:36:46 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off DE2_Default -c DE2_Default " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off DE2_Default -c DE2_Default" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "DE2_Default EP2C35F672C6 " "Info: Selected device EP2C35F672C6 for design \"DE2_Default\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Warning" "WCUT_CUT_YGR_PLL_SET_COMPENSATE_CLK" "VGA_Audio_PLL:p1\|altpll:altpll_component\|pll clock1 " "Warning: Compensate clock of PLL \"VGA_Audio_PLL:p1\|altpll:altpll_component\|pll\" has been set to clock1" {  } { { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "Compensate clock of PLL \"%1!s!\" has been set to %2!s!" 0 0}
{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "VGA_Audio_PLL:p1\|altpll:altpll_component\|pll Cyclone II " "Info: Implemented PLL \"VGA_Audio_PLL:p1\|altpll:altpll_component\|pll\" as Cyclone II PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1 2 3 0 0 " "Info: Implementing clock multiplication of 2, clock division of 3, and phase shift of 0 degrees (0 ps) for VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1 port" {  } { { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 764 3 0 } }  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk2 14 15 -90 -9921 " "Info: Implementing clock multiplication of 14, clock division of 15, and phase shift of -90 degrees (-9921 ps) for VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk2 port" {  } { { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 761 3 0 } }  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0}  } { { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "Implemented PLL \"%1!s!\" as %2!s! PLL type" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 0 "Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F672C6 " "Info: Device EP2C50F672C6 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C70F672C6 " "Info: Device EP2C70F672C6 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0}