|DE2_Default
CLOCK_27 => CLOCK_27~0.IN1
CLOCK_50 => CLOCK_50~0.IN3
EXT_CLOCK => ~NO_FANOUT~
KEY[0] => KEY[0]~0.IN1
KEY[1] => ~NO_FANOUT~
KEY[2] => ~NO_FANOUT~
KEY[3] => ~NO_FANOUT~
SW[0] => ~NO_FANOUT~
SW[1] => ~NO_FANOUT~
SW[2] => ~NO_FANOUT~
SW[3] => ~NO_FANOUT~
SW[4] => ~NO_FANOUT~
SW[5] => ~NO_FANOUT~
SW[6] => ~NO_FANOUT~
SW[7] => ~NO_FANOUT~
SW[8] => ~NO_FANOUT~
SW[9] => ~NO_FANOUT~
SW[10] => ~NO_FANOUT~
SW[11] => ~NO_FANOUT~
SW[12] => ~NO_FANOUT~
SW[13] => ~NO_FANOUT~
SW[14] => ~NO_FANOUT~
SW[15] => ~NO_FANOUT~
SW[16] => ~NO_FANOUT~
SW[17] => ~NO_FANOUT~
HEX0[0] <= <GND>
HEX0[1] <= <GND>
HEX0[2] <= <GND>
HEX0[3] <= <GND>
HEX0[4] <= <GND>
HEX0[5] <= <GND>
HEX0[6] <= <GND>
HEX1[0] <= <GND>
HEX1[1] <= <GND>
HEX1[2] <= <GND>
HEX1[3] <= <GND>
HEX1[4] <= <GND>
HEX1[5] <= <GND>
HEX1[6] <= <GND>
HEX2[0] <= <GND>
HEX2[1] <= <GND>
HEX2[2] <= <GND>
HEX2[3] <= <GND>
HEX2[4] <= <GND>
HEX2[5] <= <GND>
HEX2[6] <= <GND>
HEX3[0] <= <GND>
HEX3[1] <= <GND>
HEX3[2] <= <GND>
HEX3[3] <= <GND>
HEX3[4] <= <GND>
HEX3[5] <= <GND>
HEX3[6] <= <GND>
HEX4[0] <= <GND>
HEX4[1] <= <GND>
HEX4[2] <= <GND>
HEX4[3] <= <GND>
HEX4[4] <= <GND>
HEX4[5] <= <GND>
HEX4[6] <= <GND>
HEX5[0] <= <GND>
HEX5[1] <= <GND>
HEX5[2] <= <GND>
HEX5[3] <= <GND>
HEX5[4] <= <GND>
HEX5[5] <= <GND>
HEX5[6] <= <GND>
HEX6[0] <= <GND>
HEX6[1] <= <GND>
HEX6[2] <= <GND>
HEX6[3] <= <GND>
HEX6[4] <= <GND>
HEX6[5] <= <GND>
HEX6[6] <= <GND>
HEX7[0] <= <GND>
HEX7[1] <= <GND>
HEX7[2] <= <GND>
HEX7[3] <= <GND>
HEX7[4] <= <GND>
HEX7[5] <= <GND>
HEX7[6] <= <GND>
LEDG[0] <= LEDG~1.DB_MAX_OUTPUT_PORT_TYPE
LEDG[1] <= LEDG~0.DB_MAX_OUTPUT_PORT_TYPE
LEDG[2] <= state.0101.DB_MAX_OUTPUT_PORT_TYPE
LEDG[3] <= state.1000.DB_MAX_OUTPUT_PORT_TYPE
LEDG[4] <= <GND>
LEDG[5] <= <GND>
LEDG[6] <= <GND>
LEDG[7] <= <GND>
LEDG[8] <= <GND>
LEDR[0] <= ptr_out[0].DB_MAX_OUTPUT_PORT_TYPE
LEDR[1] <= ptr_out[1].DB_MAX_OUTPUT_PORT_TYPE
LEDR[2] <= ptr_out[2].DB_MAX_OUTPUT_PORT_TYPE
LEDR[3] <= ptr_out[3].DB_MAX_OUTPUT_PORT_TYPE
LEDR[4] <= ptr_out[4].DB_MAX_OUTPUT_PORT_TYPE
LEDR[5] <= ptr_out[5].DB_MAX_OUTPUT_PORT_TYPE
LEDR[6] <= ptr_out[6].DB_MAX_OUTPUT_PORT_TYPE
LEDR[7] <= ptr_out[7].DB_MAX_OUTPUT_PORT_TYPE
LEDR[8] <= <GND>
LEDR[9] <= <GND>
LEDR[10] <= <GND>
LEDR[11] <= <GND>
LEDR[12] <= <GND>
LEDR[13] <= <GND>
LEDR[14] <= <GND>
LEDR[15] <= <GND>
LEDR[16] <= <GND>
LEDR[17] <= <GND>
UART_TXD <= <GND>
UART_RXD => ~NO_FANOUT~
IRDA_TXD <= <GND>
IRDA_RXD => ~NO_FANOUT~
DRAM_DQ[0] <= DRAM_DQ~32
DRAM_DQ[1] <= DRAM_DQ~31
DRAM_DQ[2] <= DRAM_DQ~30
DRAM_DQ[3] <= DRAM_DQ~29
DRAM_DQ[4] <= DRAM_DQ~28
DRAM_DQ[5] <= DRAM_DQ~27
DRAM_DQ[6] <= DRAM_DQ~26
DRAM_DQ[7] <= DRAM_DQ~25
DRAM_DQ[8] <= DRAM_DQ~24
DRAM_DQ[9] <= DRAM_DQ~23
DRAM_DQ[10] <= DRAM_DQ~22
DRAM_DQ[11] <= DRAM_DQ~21
DRAM_DQ[12] <= DRAM_DQ~20
DRAM_DQ[13] <= DRAM_DQ~19
DRAM_DQ[14] <= DRAM_DQ~18
DRAM_DQ[15] <= DRAM_DQ~17
DRAM_ADDR[0] <= <GND>
DRAM_ADDR[1] <= <GND>
DRAM_ADDR[2] <= <GND>
DRAM_ADDR[3] <= <GND>
DRAM_ADDR[4] <= <GND>
DRAM_ADDR[5] <= <GND>
DRAM_ADDR[6] <= <GND>
DRAM_ADDR[7] <= <GND>
DRAM_ADDR[8] <= <GND>
DRAM_ADDR[9] <= <GND>
DRAM_ADDR[10] <= <GND>
DRAM_ADDR[11] <= <GND>
DRAM_LDQM <= <GND>
DRAM_UDQM <= <GND>
DRAM_WE_N <= <GND>
DRAM_CAS_N <= <GND>
DRAM_RAS_N <= <GND>
DRAM_CS_N <= <GND>
DRAM_BA_0 <= <GND>
DRAM_BA_1 <= <GND>
DRAM_CLK <= <GND>
DRAM_CKE <= <GND>
FL_DQ[0] <= FL_DQ~15
FL_DQ[1] <= FL_DQ~14
FL_DQ[2] <= FL_DQ~13
FL_DQ[3] <= FL_DQ~12
FL_DQ[4] <= FL_DQ~11
FL_DQ[5] <= FL_DQ~10
FL_DQ[6] <= FL_DQ~9
FL_DQ[7] <= FL_DQ~8
FL_ADDR[0] <= <GND>
FL_ADDR[1] <= <GND>
FL_ADDR[2] <= <GND>
FL_ADDR[3] <= <GND>
FL_ADDR[4] <= <GND>
FL_ADDR[5] <= <GND>
FL_ADDR[6] <= <GND>
FL_ADDR[7] <= <GND>
FL_ADDR[8] <= <GND>
FL_ADDR[9] <= <GND>
FL_ADDR[10] <= <GND>
FL_ADDR[11] <= <GND>
FL_ADDR[12] <= <GND>
FL_ADDR[13] <= <GND>
FL_ADDR[14] <= <GND>
FL_ADDR[15] <= <GND>
FL_ADDR[16] <= <GND>
FL_ADDR[17] <= <GND>
FL_ADDR[18] <= <GND>
FL_ADDR[19] <= <GND>
FL_ADDR[20] <= <GND>
FL_ADDR[21] <= <GND>
FL_WE_N <= <GND>
FL_RST_N <= <GND>
FL_OE_N <= <GND>
FL_CE_N <= <GND>
SRAM_DQ[0] <= SRAM_DQ~31
SRAM_DQ[1] <= SRAM_DQ~30
SRAM_DQ[2] <= SRAM_DQ~29
SRAM_DQ[3] <= SRAM_DQ~28
SRAM_DQ[4] <= SRAM_DQ~27
SRAM_DQ[5] <= SRAM_DQ~26
SRAM_DQ[6] <= SRAM_DQ~25
SRAM_DQ[7] <= SRAM_DQ~24
SRAM_DQ[8] <= SRAM_DQ~23
SRAM_DQ[9] <= SRAM_DQ~22
SRAM_DQ[10] <= SRAM_DQ~21
SRAM_DQ[11] <= SRAM_DQ~20
SRAM_DQ[12] <= SRAM_DQ~19
SRAM_DQ[13] <= SRAM_DQ~18
SRAM_DQ[14] <= SRAM_DQ~17
SRAM_DQ[15] <= SRAM_DQ~16
SRAM_ADDR[0] <= <GND>
SRAM_ADDR[1] <= <GND>
SRAM_ADDR[2] <= <GND>
SRAM_ADDR[3] <= <GND>
SRAM_ADDR[4] <= <GND>
SRAM_ADDR[5] <= <GND>
SRAM_ADDR[6] <= <GND>
SRAM_ADDR[7] <= <GND>
SRAM_ADDR[8] <= <GND>
SRAM_ADDR[9] <= <GND>
SRAM_ADDR[10] <= <GND>
SRAM_ADDR[11] <= <GND>
SRAM_ADDR[12] <= <GND>
SRAM_ADDR[13] <= <GND>
SRAM_ADDR[14] <= <GND>
SRAM_ADDR[15] <= <GND>
SRAM_ADDR[16] <= <GND>
SRAM_ADDR[17] <= <GND>
SRAM_UB_N <= <GND>
SRAM_LB_N <= <GND>
SRAM_WE_N <= <GND>
SRAM_CE_N <= <GND>
SRAM_OE_N <= <GND>
OTG_DATA[0] <= OTG_DATA~31
OTG_DATA[1] <= OTG_DATA~30
OTG_DATA[2] <= OTG_DATA~29
OTG_DATA[3] <= OTG_DATA~28
OTG_DATA[4] <= OTG_DATA~27
OTG_DATA[5] <= OTG_DATA~26
OTG_DATA[6] <= OTG_DATA~25
OTG_DATA[7] <= OTG_DATA~24
OTG_DATA[8] <= OTG_DATA~23
OTG_DATA[9] <= OTG_DATA~22
OTG_DATA[10] <= OTG_DATA~21
OTG_DATA[11] <= OTG_DATA~20
OTG_DATA[12] <= OTG_DATA~19
OTG_DATA[13] <= OTG_DATA~18
OTG_DATA[14] <= OTG_DATA~17
OTG_DATA[15] <= OTG_DATA~16
OTG_ADDR[0] <= <GND>
OTG_ADDR[1] <= <GND>
OTG_CS_N <= <GND>
OTG_RD_N <= <GND>
OTG_WR_N <= <GND>
OTG_RST_N <= <GND>
OTG_FSPEED <= <GND>
OTG_LSPEED <= <GND>
OTG_INT0 => ~NO_FANOUT~
OTG_INT1 => ~NO_FANOUT~
OTG_DREQ0 => ~NO_FANOUT~
OTG_DREQ1 => ~NO_FANOUT~
OTG_DACK0_N <= <GND>
OTG_DACK1_N <= <GND>
LCD_ON <= <GND>
LCD_BLON <= <GND>
LCD_RW <= <GND>
LCD_EN <= <GND>
LCD_RS <= <GND>
LCD_DATA[0] <= <UNC>
LCD_DATA[1] <= <UNC>
LCD_DATA[2] <= <UNC>
LCD_DATA[3] <= <UNC>
LCD_DATA[4] <= <UNC>
LCD_DATA[5] <= <UNC>
LCD_DATA[6] <= <UNC>
LCD_DATA[7] <= <UNC>
SD_DAT <= SD_DAT~0
SD_DAT3 <= <UNC>
SD_CMD <= <UNC>
SD_CLK <= <GND>
TDI => ~NO_FANOUT~
TCK => ~NO_FANOUT~
TCS => ~NO_FANOUT~
TDO <= <GND>
I2C_SDAT <= I2C_AV_Config:u3.I2C_SDAT
I2C_SCLK <= I2C_AV_Config:u3.I2C_SCLK
PS2_DAT => ~NO_FANOUT~
PS2_CLK => ~NO_FANOUT~
VGA_CLK <= VGA_Audio_PLL:p1.c2
VGA_HS <= <GND>
VGA_VS <= <GND>
VGA_BLANK <= <GND>
VGA_SYNC <= <GND>
VGA_R[0] <= <GND>
VGA_R[1] <= <GND>
VGA_R[2] <= <GND>
VGA_R[3] <= <GND>
VGA_R[4] <= <GND>
VGA_R[5] <= <GND>
VGA_R[6] <= <GND>
VGA_R[7] <= <GND>
VGA_R[8] <= <GND>
VGA_R[9] <= <GND>
VGA_G[0] <= <GND>
VGA_G[1] <= <GND>
VGA_G[2] <= <GND>
VGA_G[3] <= <GND>
VGA_G[4] <= <GND>
VGA_G[5] <= <GND>
VGA_G[6] <= <GND>
VGA_G[7] <= <GND>
VGA_G[8] <= <GND>
VGA_G[9] <= <GND>
VGA_B[0] <= <GND>
VGA_B[1] <= <GND>
VGA_B[2] <= <GND>
VGA_B[3] <= <GND>
VGA_B[4] <= <GND>
VGA_B[5] <= <GND>
VGA_B[6] <= <GND>
VGA_B[7] <= <GND>
VGA_B[8] <= <GND>
VGA_B[9] <= <GND>
ENET_DATA[0] <= ENET_DATA~31
ENET_DATA[1] <= ENET_DATA~30
ENET_DATA[2] <= ENET_DATA~29
ENET_DATA[3] <= ENET_DATA~28
ENET_DATA[4] <= ENET_DATA~27
ENET_DATA[5] <= ENET_DATA~26
ENET_DATA[6] <= ENET_DATA~25
ENET_DATA[7] <= ENET_DATA~24
ENET_DATA[8] <= ENET_DATA~23
ENET_DATA[9] <= ENET_DATA~22
ENET_DATA[10] <= ENET_DATA~21
ENET_DATA[11] <= ENET_DATA~20
ENET_DATA[12] <= ENET_DATA~19
ENET_DATA[13] <= ENET_DATA~18
ENET_DATA[14] <= ENET_DATA~17
ENET_DATA[15] <= ENET_DATA~16
ENET_CMD <= <GND>
ENET_CS_N <= <GND>
ENET_WR_N <= <GND>
ENET_RD_N <= <GND>
ENET_RST_N <= <GND>
ENET_INT => ~NO_FANOUT~
ENET_CLK <= <GND>
AUD_ADCLRCK <= AUDIO_DAC_ADC:u4.oAUD_LRCK
AUD_ADCDAT => AUD_ADCDAT~0.IN1
AUD_DACLRCK <= AUDIO_DAC_ADC:u4.oAUD_LRCK
AUD_DACDAT <= AUDIO_DAC_ADC:u4.oAUD_DATA
AUD_BCLK <= AUDIO_DAC_ADC:u4.oAUD_BCK
AUD_XCK <= AUD_CTRL_CLK.DB_MAX_OUTPUT_PORT_TYPE
TD_DATA[0] => ~NO_FANOUT~
TD_DATA[1] => ~NO_FANOUT~
TD_DATA[2] => ~NO_FANOUT~
TD_DATA[3] => ~NO_FANOUT~
TD_DATA[4] => ~NO_FANOUT~
TD_DATA[5] => ~NO_FANOUT~
TD_DATA[6] => ~NO_FANOUT~
TD_DATA[7] => ~NO_FANOUT~
TD_HS => ~NO_FANOUT~
TD_VS => ~NO_FANOUT~
TD_RESET <= <VCC>
GPIO_0[0] <= GPIO_0~71
GPIO_0[1] <= GPIO_0~70
GPIO_0[2] <= GPIO_0~69
GPIO_0[3] <= GPIO_0~68
GPIO_0[4] <= GPIO_0~67
GPIO_0[5] <= GPIO_0~66
GPIO_0[6] <= GPIO_0~65
GPIO_0[7] <= GPIO_0~64
GPIO_0[8] <= GPIO_0~63
GPIO_0[9] <= GPIO_0~62
GPIO_0[10] <= GPIO_0~61
GPIO_0[11] <= GPIO_0~60
GPIO_0[12] <= GPIO_0~59
GPIO_0[13] <= GPIO_0~58
GPIO_0[14] <= GPIO_0~57
GPIO_0[15] <= GPIO_0~56
GPIO_0[16] <= GPIO_0~55
GPIO_0[17] <= GPIO_0~54
GPIO_0[18] <= GPIO_0~53
GPIO_0[19] <= GPIO_0~52
GPIO_0[20] <= GPIO_0~51
GPIO_0[21] <= GPIO_0~50
GPIO_0[22] <= GPIO_0~49
GPIO_0[23] <= GPIO_0~48
GPIO_0[24] <= GPIO_0~47
GPIO_0[25] <= GPIO_0~46
GPIO_0[26] <= GPIO_0~45
GPIO_0[27] <= GPIO_0~44
GPIO_0[28] <= GPIO_0~43
GPIO_0[29] <= GPIO_0~42
GPIO_0[30] <= GPIO_0~41
GPIO_0[31] <= GPIO_0~40
GPIO_0[32] <= GPIO_0~39
GPIO_0[33] <= GPIO_0~38
GPIO_0[34] <= GPIO_0~37
GPIO_0[35] <= GPIO_0~36
GPIO_1[0] <= GPIO_1~71
GPIO_1[1] <= GPIO_1~70
GPIO_1[2] <= GPIO_1~69
GPIO_1[3] <= GPIO_1~68
GPIO_1[4] <= GPIO_1~67
GPIO_1[5] <= GPIO_1~66
GPIO_1[6] <= GPIO_1~65
GPIO_1[7] <= GPIO_1~64
GPIO_1[8] <= GPIO_1~63
GPIO_1[9] <= GPIO_1~62
GPIO_1[10] <= GPIO_1~61
GPIO_1[11] <= GPIO_1~60
GPIO_1[12] <= GPIO_1~59
GPIO_1[13] <= GPIO_1~58
GPIO_1[14] <= GPIO_1~57
GPIO_1[15] <= GPIO_1~56
GPIO_1[16] <= GPIO_1~55
GPIO_1[17] <= GPIO_1~54
GPIO_1[18] <= GPIO_1~53
GPIO_1[19] <= GPIO_1~52
GPIO_1[20] <= GPIO_1~51
GPIO_1[21] <= GPIO_1~50
GPIO_1[22] <= GPIO_1~49
GPIO_1[23] <= GPIO_1~48
GPIO_1[24] <= GPIO_1~47
GPIO_1[25] <= GPIO_1~46
GPIO_1[26] <= GPIO_1~45
GPIO_1[27] <= GPIO_1~44
GPIO_1[28] <= GPIO_1~43
GPIO_1[29] <= GPIO_1~42
GPIO_1[30] <= GPIO_1~41
GPIO_1[31] <= GPIO_1~40
GPIO_1[32] <= GPIO_1~39
GPIO_1[33] <= GPIO_1~38
GPIO_1[34] <= GPIO_1~37
GPIO_1[35] <= GPIO_1~36


|DE2_Default|Reset_Delay:r0
iCLK => Cont[18].CLK
iCLK => Cont[17].CLK
iCLK => Cont[16].CLK
iCLK => Cont[15].CLK
iCLK => Cont[14].CLK
iCLK => Cont[13].CLK
iCLK => Cont[12].CLK
iCLK => Cont[11].CLK
iCLK => Cont[10].CLK
iCLK => Cont[9].CLK
iCLK => Cont[8].CLK
iCLK => Cont[7].CLK
iCLK => Cont[6].CLK
iCLK => Cont[5].CLK
iCLK => Cont[4].CLK
iCLK => Cont[3].CLK
iCLK => Cont[2].CLK
iCLK => Cont[1].CLK
iCLK => Cont[0].CLK
iCLK => oRESET~reg0.CLK
iCLK => Cont[19].CLK
oRESET <= oRESET~reg0.DB_MAX_OUTPUT_PORT_TYPE


|DE2_Default|VGA_Audio_PLL:p1
areset => areset~0.IN1
inclk0 => sub_wire5[0].IN1
c0 <= altpll:altpll_component.clk
c1 <= altpll:altpll_component.clk
c2 <= altpll:altpll_component.clk


|DE2_Default|VGA_Audio_PLL:p1|altpll:altpll_component
inclk[0] => pll.CLK
inclk[1] => pll.CLK1
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => pll.ARESET
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
clk[0] <= pll.CLK
clk[1] <= pll.CLK1
clk[2] <= pll.CLK2
clk[3] <= <UNC>
clk[4] <= <UNC>
clk[5] <= <UNC>
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>