library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity aa is
port( a: in unsigned(3 downto 0);
   b: in unsigned(3 downto 0);
   cin:in std_logic;
   bcdout: out std_logic_vector(3 downto 0);
   cout:out std_logic );
end aa;
architecture arch of aa is
  signal co,y:std_logic_vector(3 downto 0);
  begin
    y(0)<=a(0)xor b(0)xor cin;
    co(0)<=(a(0)and b(0))or(b(0)and cin)or(a(0)and cin);
      gen:for I in 1 to 3 generate
       y(I)<=a(I)xor b(I)xor co(I-1);
       co(I)<=(co(I-1)and a(I)) or (co(I-1)and b(I))or (a(I)and b(I));
end generate;
bcdout<=y(3)&y(2)&y(1)&y(0);
cout<=co(3);
end arch;