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/*
* armboot - Startup Code for ARM920 CPU-core
*
* Copyright (c) 2001 Marius Gr榘僥r <mag@sysgo.de>
* Copyright (c) 2002 Alex Z榛砶e <azu@sysgo.de>
* Copyright (c) 2002 Gary Jennejohn <gj@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#if defined(CONFIG_S3C2400)
#define pWTCON 0x15300000
#define INTMSK 0x14400008 /* Interupt-Controller base addresses */
#define CLKDIVN 0x14800014 /* clock divisor register */
#elif defined(CONFIG_S3C2410)
#define pWTCON 0x53000000
#define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
#define INTSUBMSK 0x4A00001C
#define CLKDIVN 0x4C000014 /* clock divisor register */
#elif defined(CONFIG_S3C2440) /*new*/
#define pWTCON 0x53000000
#define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
#define INTSUBMSK 0x4A00001C
#define CLKDIVN 0x4C000014 /* clock divisor register */ /*new*/
#define CONFIG_S3C2440_NAND_BOOT 1
#define NAND_CTL_BASE 0x4e000000
/*#define oNFCONF 0x00*/
/*#define oNFCMD 0x04*/
/*#define oNFADDR 0x08*/
/*#define oNFDATA 0x0c*/
/*#define oNFSTAT 0x10*/
/*#define oNFECC 0x14*/
/*Offset*/
#define oNFCONF 0x00
#define oNFCONT 0x04 /*new*/
#define oNFCMD 0x08
#define oNFADDR 0x0c
#define oNFDATA 0x010
#define oNFSTAT 0x20
#define oNFECC 0x14
#define UBase 0x50000000
#define oUTRSTAT 0x10
#define UTRSTAT_TX_EMPTY (1<<2)
#define oUTXHL 0x20
#define oULCON 0x00
#define oUCON 0x04
#define oUFCON 0x08
#define oUMCON 0x0c
/*#define vUART_FREQ 50750000*/ /*new*/
/*UBRDIVn = (int)( UART clock / ( buad rate x 16) ) –1*/
/*UART clock=Pclk=Fclk/6 CLKDIV=7 Fclk=296352000 Fclk:Hclk:Pclk=1:3:6*/
/*((vUART_FREQ/(UART_BAUD_RATE * 16))-1)=25.796875*/
#define vUART_FREQ 49392000
#define UART_BAUD_RATE 115200
#define UART_BRD 26
#define oUBRDIV 0x28
#define TACLS 7 // 1-clk(0ns)
#define TWRPH0 7 // 3-clk(25ns)
#define TWRPH1 7 // 1-clk(10ns) //TACLS+TWRPH0
#endif
#if defined(CONFIG_S3C2440)
#define CONFIG_DEBUG_LL 1
#define UART0_CTL_BASE 0x50000000
SerBase:
#if defined(CONFIG_S3C2440)
.long UART0_CTL_BASE
#endif
#define SZ_64M 0x04000000
#define SZ_1M 0x00100000
#define SZ_16K 0x00004000
#define SZ_32K 0x00008000
#define DRAM_BASE0 0x30000000 /* base address of dram bank 0 */
#define DRAM_BASE1 0x38000000 /* base address of dram bank 1 */
#define DRAM_BASE DRAM_BASE0
#define DRAM_SIZE SZ_64M
#define MTD_PART_SIZE SZ_16K
#define MTD_PART_OFFSET 0x00000000
#define PARAMETER_TLB_SIZE SZ_16K
#define PARAMETER_TLB_OFFSET 0x00004000
#define LINUX_CMD_SIZE SZ_16K
#define LINUX_CMD_OFFSET 0x00008000
#define VIVI_PRIV_SIZE (MTD_PART_SIZE + PARAMETER_TLB_SIZE + LINUX_CMD_SIZE)
/* RAM */
#define VIVI_RAM_SIZE SZ_1M
#define VIVI_RAM_BASE (DRAM_BASE + DRAM_SIZE - VIVI_RAM_SIZE)
#define HEAP_SIZE SZ_1M
#define HEAP_BASE (VIVI_RAM_BASE - HEAP_SIZE)
#define MMU_TABLE_SIZE SZ_16K
#define MMU_TABLE_BASE (HEAP_BASE - MMU_TABLE_SIZE)
#define VIVI_PRIV_RAM_BASE (MMU_TABLE_BASE - VIVI_PRIV_SIZE)
#define STACK_SIZE SZ_32K
#define STACK_BASE (VIVI_PRIV_RAM_BASE - STACK_SIZE)
#define RAM_SIZE (STACK_BASE - DRAM_BASE)
#define RAM_BASE DRAM_BASE
#endif
/*
*************************************************************************
*
* Jump vector table as in table 3.1 in [1]
*
*************************************************************************
*/
.equ PSR_MODE_USR, 0x10
.equ PSR_MODE_FIQ, 0x11
.equ PSR_MODE_IRQ, 0x12
.equ PSR_MODE_SVC, 0x13
.equ PSR_MODE_ABT, 0x17
.equ PSR_MODE_UNDEF, 0x1B
.equ PSR_MODE_SYS, 0x1F
.equ PSR_I, 0x80
.equ PSR_F, 0x40
.equ PSR_T, 0x20
.globl _start
_start: b reset
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
ldr pc, _data_abort
ldr pc, _not_used
ldr pc, _irq
ldr pc, _fiq
_undefined_instruction: .word undefined_instruction
_software_interrupt: .word software_interrupt
_prefetch_abort: .word prefetch_abort
_data_abort: .word data_abort
_not_used: .word not_used
_irq: .word irq
_fiq: .word fiq
.balignl 16,0xdeadbeef
/*
*************************************************************************
*
* Startup Code (reset vector)
*
* do important init only if we don't start from memory!
* relocate armboot to ram
* setup stack
* jump to second stage
*
*************************************************************************
*/
_TEXT_BASE:
.word TEXT_BASE
.globl _armboot_start
_armboot_start:
.word _start
/*
* These are defined in the board-specific linker script.
*/
.globl _bss_start
_bss_start:
.word __bss_start
.globl _bss_end
_bss_end:
.word _end
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
.word 0x0badc0de
/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
.word 0x0badc0de
#endif
/*
* the actual reset code
*/
reset:
#if defined(CONFIG_S3C2440) /*new*/
ldr r0,=0x56000050 /*TEST:before entering stage2,we turn on led as 1111*/
ldr r1,=0x5500 /*new*/
str r1,[r0] /*new*/
ldr r0,=0x56000054 /*new*/
ldr r1,=0x00 /*new*/
str r1,[r0] /*new*/
#endif /*new*/
mrs r0, cpsr
bic r0, r0, #0x1f
orr r0, r0, #0xd3
msr cpsr, r0
mov r1, #0x53000000
mov r2, #0x0
str r2, [r1]
mov r1, #0xffffffff
ldr r0, =INTMSK
str r1, [r0]
/*ldr r1, =0x3ff*/ /*new*/
/*ldr r1, =0xffff*/ /*new*/
ldr r1, =0x7ff
ldr r0, =INTSUBMSK
str r1, [r0]
mov r1, #0x4c000000
mvn r2, #0xff000000
str r2, [r1, #0]
mov r1, #0x4c000000
/*mov r2, #0x3*/
mov r2, #0x7 /*new*/
str r2, [r1, #0x14]
mrc p15, 0, r1, c1, c0, 0 @ read ctrl register
orr r1, r1, #0xc0000000 @ Asynchronous
mcr p15, 0, r1, c1, c0, 0 @ write ctrl register
/*
U_MDIV EQU 60 ;Fin=16.9344MHz Fout=96MHz
U_PDIV EQU 4
U_SDIV EQU 1*/
mov r1, #0X4C000000 /*new*/
ldr r2, =(0X3c<<12)|(0X4<<4)|(1) /*new*/
str r2, [r1, #0X8] /*new*/
nop
nop
nop
nop
nop
nop
nop
/*
M_MDIV EQU 97 ;Fin=16.9344MHz
M_PDIV EQU 1
[ CPU_SEL = 32440001
M_SDIV EQU 2 ; 2440A
|
M_SDIV EQU 1 ; 2440X
]
*/
mov r1, #0X4C000000
/*ldr r2, =(0X5C<<12)|(0X4<<4)|(0)*/ /*new*/
ldr r2, =(0X61<<12)|(0X1<<4)|(2)
str r2, [r1, #0X4]
bl cpu_init_crit
#if 1
/*GPHCON GPGCON設置*/ /*new*/
mov r1, #0x56000000
add r1, r1, #0x70
ldr r2, =0x0016faaa
str r2, [r1,#0]
ldr r2, =0x000007ff
str r2, [r1, #0x8]
#else
/*Push UART GPIO port configuration*/
mov r1, #0x56000000 /*GPHCON*/
ldr r2, [r1, #0x70]
and r2, r2, #0x3c0000
//orr r2, r2, #0x2aaaa /*enable all uart channel*/
orr r2, r2, #0xaa
orr r2, r2, #0xaa00
orr r2, r2, #0x20000
str r2, [r1,#0x70]
ldr r2, [r1, #0x78]
//orr r2, r2, #0x1ff /*Uart port pull-up disable*/
orr r2, r2, #0xff
orr r2, r2, #0x100
str r2, [r1,#0x78]
#endif
#if 0
ldr r2, [r1, #0x60] /*GPGCON*/ /*new*/
orr r2, r2, #0x3c0000
str r2, [r1,#0x60]
ldr r2, [r1, #0x68]
orr r2, r2, #0x600
str r2, [r1,#0x68]
#endif
bl InitUART
#ifdef CONFIG_DEBUG_LL
mov r0, #'\r'
bl PrintChar
mov r0, #'\n'
bl PrintChar
mov r0, #'S'
bl PrintChar
//ldr r0, =0x5050f0f0
//bl PrintHexWord
mov r0, pc
bl PrintHexWord
#endif
#ifdef CONFIG_DEBUG_LL /*new*/
ldr r0,=0x56000050 /*TEST:before entering stage2,we turn off led as 1100*/
ldr r1,=0x5500 /*new*/
str r1,[r0] /*new*/
ldr r0,=0x56000054 /*new*/
ldr r1,=0xc0 /*new*/
str r1,[r0] /*new*/
#endif
#ifdef CONFIG_S3C2440_NAND_BOOT
bl copy_myself
#if 1
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
sub sp, r0, #12 /* leave 3 words for abort-stack */
clear_bss:
ldr r0, _bss_start /* find start of bss segment */
ldr r1, _bss_end /* stop here */
mov r2, #0x00000000 /* clear */
clbss_l:str r2, [r0] /* clear loop... */
add r0, r0, #4
cmp r0, r1
ble clbss_l
#endif
#if 0
mov r1, #0x56000000
add r1, r1, #0x10
ldr r2, =0x044555
str r2, [r1, #0x0]
mov r2, #0xff
str r2, [r1, #0x8]
mov r2, #0x3
str r2, [r1, #0x4]
#endif
ldr r5, _start_armboot
#ifdef CONFIG_DEBUG_LL
mov r0, #'\r'
bl PrintChar
mov r0, #'\n'
bl PrintChar
mov r0, r5
bl PrintHexWord
/*new*/
ldr r2,=0x56000050 /*TEST:before entering stage2,we turn off led as 1001*/
ldr r3,=0x5500 /*new*/
str r3,[r2] /*new*/
ldr r2,=0x56000054 /*new*/
ldr r3,=0x90 /*new*/
str r3,[r2] /*new*/
mov r0, #'\r'
bl PrintChar
mov r0, #'\n'
bl PrintChar
mov r0, #'S'
bl PrintChar
mov r0, #'T'
bl PrintChar
mov r0, #'A'
bl PrintChar
mov r0, #'G'
bl PrintChar
mov r0, #'E'
bl PrintChar
mov r0, #'1'
bl PrintChar
mov r0, #'E'
bl PrintChar
mov r0, #'N'
bl PrintChar
mov r0, #'D'
bl PrintChar
#endif
#ifdef CONFIG_DEBUG_LL
ldr r1, SerBase
ldr r0, STR_STACK
bl PrintWord
ldr r0, DW_STACK_START
bl PrintHexWord
#endif
@ get read to call C functions
ldr sp, DW_STACK_START @ setup stack pointer
mov fp, #0 @ no previous frame, so fp=0
mov a2, #0 @ set argv to NULL
@ jump to ram
ldr r1, =on_the_ram
add pc, r1, #0
nop
nop
1: b 1b @ infinite loop
on_the_ram:
#endif
ldr pc, _start_armboot
_start_armboot: .word start_armboot
#ifdef CONFIG_S3C2440_NAND_BOOT
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