?? at91sam7x256.tcl
字號:
set AT91C_UDP_EPINT0 [expr 0x1 << 0 ]
set AT91C_UDP_EPINT1 [expr 0x1 << 1 ]
set AT91C_UDP_EPINT2 [expr 0x1 << 2 ]
set AT91C_UDP_EPINT3 [expr 0x1 << 3 ]
set AT91C_UDP_EPINT4 [expr 0x1 << 4 ]
set AT91C_UDP_EPINT5 [expr 0x1 << 5 ]
set AT91C_UDP_RXSUSP [expr 0x1 << 8 ]
set AT91C_UDP_RXRSM [expr 0x1 << 9 ]
set AT91C_UDP_EXTRSM [expr 0x1 << 10 ]
set AT91C_UDP_SOFINT [expr 0x1 << 11 ]
set AT91C_UDP_WAKEUP [expr 0x1 << 13 ]
# -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
set AT91C_UDP_EPINT0 [expr 0x1 << 0 ]
set AT91C_UDP_EPINT1 [expr 0x1 << 1 ]
set AT91C_UDP_EPINT2 [expr 0x1 << 2 ]
set AT91C_UDP_EPINT3 [expr 0x1 << 3 ]
set AT91C_UDP_EPINT4 [expr 0x1 << 4 ]
set AT91C_UDP_EPINT5 [expr 0x1 << 5 ]
set AT91C_UDP_RXSUSP [expr 0x1 << 8 ]
set AT91C_UDP_RXRSM [expr 0x1 << 9 ]
set AT91C_UDP_EXTRSM [expr 0x1 << 10 ]
set AT91C_UDP_SOFINT [expr 0x1 << 11 ]
set AT91C_UDP_WAKEUP [expr 0x1 << 13 ]
# -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
set AT91C_UDP_EPINT0 [expr 0x1 << 0 ]
set AT91C_UDP_EPINT1 [expr 0x1 << 1 ]
set AT91C_UDP_EPINT2 [expr 0x1 << 2 ]
set AT91C_UDP_EPINT3 [expr 0x1 << 3 ]
set AT91C_UDP_EPINT4 [expr 0x1 << 4 ]
set AT91C_UDP_EPINT5 [expr 0x1 << 5 ]
set AT91C_UDP_RXSUSP [expr 0x1 << 8 ]
set AT91C_UDP_RXRSM [expr 0x1 << 9 ]
set AT91C_UDP_EXTRSM [expr 0x1 << 10 ]
set AT91C_UDP_SOFINT [expr 0x1 << 11 ]
set AT91C_UDP_WAKEUP [expr 0x1 << 13 ]
# -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
set AT91C_UDP_EPINT0 [expr 0x1 << 0 ]
set AT91C_UDP_EPINT1 [expr 0x1 << 1 ]
set AT91C_UDP_EPINT2 [expr 0x1 << 2 ]
set AT91C_UDP_EPINT3 [expr 0x1 << 3 ]
set AT91C_UDP_EPINT4 [expr 0x1 << 4 ]
set AT91C_UDP_EPINT5 [expr 0x1 << 5 ]
set AT91C_UDP_RXSUSP [expr 0x1 << 8 ]
set AT91C_UDP_RXRSM [expr 0x1 << 9 ]
set AT91C_UDP_EXTRSM [expr 0x1 << 10 ]
set AT91C_UDP_SOFINT [expr 0x1 << 11 ]
set AT91C_UDP_ENDBUSRES [expr 0x1 << 12 ]
set AT91C_UDP_WAKEUP [expr 0x1 << 13 ]
# -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
set AT91C_UDP_EPINT0 [expr 0x1 << 0 ]
set AT91C_UDP_EPINT1 [expr 0x1 << 1 ]
set AT91C_UDP_EPINT2 [expr 0x1 << 2 ]
set AT91C_UDP_EPINT3 [expr 0x1 << 3 ]
set AT91C_UDP_EPINT4 [expr 0x1 << 4 ]
set AT91C_UDP_EPINT5 [expr 0x1 << 5 ]
set AT91C_UDP_RXSUSP [expr 0x1 << 8 ]
set AT91C_UDP_RXRSM [expr 0x1 << 9 ]
set AT91C_UDP_EXTRSM [expr 0x1 << 10 ]
set AT91C_UDP_SOFINT [expr 0x1 << 11 ]
set AT91C_UDP_WAKEUP [expr 0x1 << 13 ]
# -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
set AT91C_UDP_EP0 [expr 0x1 << 0 ]
set AT91C_UDP_EP1 [expr 0x1 << 1 ]
set AT91C_UDP_EP2 [expr 0x1 << 2 ]
set AT91C_UDP_EP3 [expr 0x1 << 3 ]
set AT91C_UDP_EP4 [expr 0x1 << 4 ]
set AT91C_UDP_EP5 [expr 0x1 << 5 ]
# -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
set AT91C_UDP_TXCOMP [expr 0x1 << 0 ]
set AT91C_UDP_RX_DATA_BK0 [expr 0x1 << 1 ]
set AT91C_UDP_RXSETUP [expr 0x1 << 2 ]
set AT91C_UDP_ISOERROR [expr 0x1 << 3 ]
set AT91C_UDP_TXPKTRDY [expr 0x1 << 4 ]
set AT91C_UDP_FORCESTALL [expr 0x1 << 5 ]
set AT91C_UDP_RX_DATA_BK1 [expr 0x1 << 6 ]
set AT91C_UDP_DIR [expr 0x1 << 7 ]
set AT91C_UDP_EPTYPE [expr 0x7 << 8 ]
set AT91C_UDP_EPTYPE_CTRL [expr 0x0 << 8 ]
set AT91C_UDP_EPTYPE_ISO_OUT [expr 0x1 << 8 ]
set AT91C_UDP_EPTYPE_BULK_OUT [expr 0x2 << 8 ]
set AT91C_UDP_EPTYPE_INT_OUT [expr 0x3 << 8 ]
set AT91C_UDP_EPTYPE_ISO_IN [expr 0x5 << 8 ]
set AT91C_UDP_EPTYPE_BULK_IN [expr 0x6 << 8 ]
set AT91C_UDP_EPTYPE_INT_IN [expr 0x7 << 8 ]
set AT91C_UDP_DTGLE [expr 0x1 << 11 ]
set AT91C_UDP_EPEDS [expr 0x1 << 15 ]
set AT91C_UDP_RXBYTECNT [expr 0x7FF << 16 ]
# -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
set AT91C_UDP_TXVDIS [expr 0x1 << 8 ]
set AT91C_UDP_PUON [expr 0x1 << 9 ]
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
# *****************************************************************************
# -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
set AT91C_TC_CLKEN [expr 0x1 << 0 ]
set AT91C_TC_CLKDIS [expr 0x1 << 1 ]
set AT91C_TC_SWTRG [expr 0x1 << 2 ]
# -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
set AT91C_TC_CLKS [expr 0x7 << 0 ]
set AT91C_TC_CLKS_TIMER_DIV1_CLOCK 0x0
set AT91C_TC_CLKS_TIMER_DIV2_CLOCK 0x1
set AT91C_TC_CLKS_TIMER_DIV3_CLOCK 0x2
set AT91C_TC_CLKS_TIMER_DIV4_CLOCK 0x3
set AT91C_TC_CLKS_TIMER_DIV5_CLOCK 0x4
set AT91C_TC_CLKS_XC0 0x5
set AT91C_TC_CLKS_XC1 0x6
set AT91C_TC_CLKS_XC2 0x7
set AT91C_TC_CLKS [expr 0x7 << 0 ]
set AT91C_TC_CLKS_TIMER_DIV1_CLOCK 0x0
set AT91C_TC_CLKS_TIMER_DIV2_CLOCK 0x1
set AT91C_TC_CLKS_TIMER_DIV3_CLOCK 0x2
set AT91C_TC_CLKS_TIMER_DIV4_CLOCK 0x3
set AT91C_TC_CLKS_TIMER_DIV5_CLOCK 0x4
set AT91C_TC_CLKS_XC0 0x5
set AT91C_TC_CLKS_XC1 0x6
set AT91C_TC_CLKS_XC2 0x7
set AT91C_TC_CLKI [expr 0x1 << 3 ]
set AT91C_TC_CLKI [expr 0x1 << 3 ]
set AT91C_TC_BURST [expr 0x3 << 4 ]
set AT91C_TC_BURST_NONE [expr 0x0 << 4 ]
set AT91C_TC_BURST_XC0 [expr 0x1 << 4 ]
set AT91C_TC_BURST_XC1 [expr 0x2 << 4 ]
set AT91C_TC_BURST_XC2 [expr 0x3 << 4 ]
set AT91C_TC_BURST [expr 0x3 << 4 ]
set AT91C_TC_BURST_NONE [expr 0x0 << 4 ]
set AT91C_TC_BURST_XC0 [expr 0x1 << 4 ]
set AT91C_TC_BURST_XC1 [expr 0x2 << 4 ]
set AT91C_TC_BURST_XC2 [expr 0x3 << 4 ]
set AT91C_TC_CPCSTOP [expr 0x1 << 6 ]
set AT91C_TC_LDBSTOP [expr 0x1 << 6 ]
set AT91C_TC_LDBDIS [expr 0x1 << 7 ]
set AT91C_TC_CPCDIS [expr 0x1 << 7 ]
set AT91C_TC_ETRGEDG [expr 0x3 << 8 ]
set AT91C_TC_ETRGEDG_NONE [expr 0x0 << 8 ]
set AT91C_TC_ETRGEDG_RISING [expr 0x1 << 8 ]
set AT91C_TC_ETRGEDG_FALLING [expr 0x2 << 8 ]
set AT91C_TC_ETRGEDG_BOTH [expr 0x3 << 8 ]
set AT91C_TC_EEVTEDG [expr 0x3 << 8 ]
set AT91C_TC_EEVTEDG_NONE [expr 0x0 << 8 ]
set AT91C_TC_EEVTEDG_RISING [expr 0x1 << 8 ]
set AT91C_TC_EEVTEDG_FALLING [expr 0x2 << 8 ]
set AT91C_TC_EEVTEDG_BOTH [expr 0x3 << 8 ]
set AT91C_TC_ABETRG [expr 0x1 << 10 ]
set AT91C_TC_EEVT [expr 0x3 << 10 ]
set AT91C_TC_EEVT_TIOB [expr 0x0 << 10 ]
set AT91C_TC_EEVT_XC0 [expr 0x1 << 10 ]
set AT91C_TC_EEVT_XC1 [expr 0x2 << 10 ]
set AT91C_TC_EEVT_XC2 [expr 0x3 << 10 ]
set AT91C_TC_ENETRG [expr 0x1 << 12 ]
set AT91C_TC_WAVESEL [expr 0x3 << 13 ]
set AT91C_TC_WAVESEL_UP [expr 0x0 << 13 ]
set AT91C_TC_WAVESEL_UPDOWN [expr 0x1 << 13 ]
set AT91C_TC_WAVESEL_UP_AUTO [expr 0x2 << 13 ]
set AT91C_TC_WAVESEL_UPDOWN_AUTO [expr 0x3 << 13 ]
set AT91C_TC_CPCTRG [expr 0x1 << 14 ]
set AT91C_TC_WAVE [expr 0x1 << 15 ]
set AT91C_TC_WAVE [expr 0x1 << 15 ]
set AT91C_TC_LDRA [expr 0x3 << 16 ]
set AT91C_TC_LDRA_NONE [expr 0x0 << 16 ]
set AT91C_TC_LDRA_RISING [expr 0x1 << 16 ]
set AT91C_TC_LDRA_FALLING [expr 0x2 << 16 ]
set AT91C_TC_LDRA_BOTH [expr 0x3 << 16 ]
set AT91C_TC_ACPA [expr 0x3 << 16 ]
set AT91C_TC_ACPA_NONE [expr 0x0 << 16 ]
set AT91C_TC_ACPA_SET [expr 0x1 << 16 ]
set AT91C_TC_ACPA_CLEAR [expr 0x2 << 16 ]
set AT91C_TC_ACPA_TOGGLE [expr 0x3 << 16 ]
set AT91C_TC_LDRB [expr 0x3 << 18 ]
set AT91C_TC_LDRB_NONE [expr 0x0 << 18 ]
set AT91C_TC_LDRB_RISING [expr 0x1 << 18 ]
set AT91C_TC_LDRB_FALLING [expr 0x2 << 18 ]
set AT91C_TC_LDRB_BOTH [expr 0x3 << 18 ]
set AT91C_TC_ACPC [expr 0x3 << 18 ]
set AT91C_TC_ACPC_NONE [expr 0x0 << 18 ]
set AT91C_TC_ACPC_SET [expr 0x1 << 18 ]
set AT91C_TC_ACPC_CLEAR [expr 0x2 << 18 ]
set AT91C_TC_ACPC_TOGGLE [expr 0x3 << 18 ]
set AT91C_TC_AEEVT [expr 0x3 << 20 ]
set AT91C_TC_AEEVT_NONE [expr 0x0 << 20 ]
set AT91C_TC_AEEVT_SET [expr 0x1 << 20 ]
set AT91C_TC_AEEVT_CLEAR [expr 0x2 << 20 ]
set AT91C_TC_AEEVT_TOGGLE [expr 0x3 << 20 ]
set AT91C_TC_ASWTRG [expr 0x3 << 22 ]
set AT91C_TC_ASWTRG_NONE [expr 0x0 << 22 ]
set AT91C_TC_ASWTRG_SET [expr 0x1 << 22 ]
set AT91C_TC_ASWTRG_CLEAR [expr 0x2 << 22 ]
set AT91C_TC_ASWTRG_TOGGLE [expr 0x3 << 22 ]
set AT91C_TC_BCPB [expr 0x3 << 24 ]
set AT91C_TC_BCPB_NONE [expr 0x0 << 24 ]
set AT91C_TC_BCPB_SET [expr 0x1 << 24 ]
set AT91C_TC_BCPB_CLEAR [expr 0x2 << 24 ]
set AT91C_TC_BCPB_TOGGLE [expr 0x3 << 24 ]
set AT91C_TC_BCPC [expr 0x3 << 26 ]
set AT91C_TC_BCPC_NONE [expr 0x0 << 26 ]
set AT91C_TC_BCPC_SET [expr 0x1 << 26 ]
set AT91C_TC_BCPC_CLEAR [expr 0x2 << 26 ]
set AT91C_TC_BCPC_TOGGLE [expr 0x3 << 26 ]
set AT91C_TC_BEEVT [expr 0x3 << 28 ]
set AT91C_TC_BEEVT_NONE [expr 0x0 << 28 ]
set AT91C_TC_BEEVT_SET [expr 0x1 << 28 ]
set AT91C_TC_BEEVT_CLEAR [expr 0x2 << 28 ]
set AT91C_TC_BEEVT_TOGGLE [expr 0x3 << 28 ]
set AT91C_TC_BSWTRG [expr 0x3 << 30 ]
set AT91C_TC_BSWTRG_NONE [expr 0x0 << 30 ]
set AT91C_TC_BSWTRG_SET [expr 0x1 << 30 ]
set AT91C_TC_BSWTRG_CLEAR [expr 0x2 << 30 ]
set AT91C_TC_BSWTRG_TOGGLE [expr 0x3 << 30 ]
# -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
set AT91C_TC_COVFS [expr 0x1 << 0 ]
set AT91C_TC_LOVRS [expr 0x1 << 1 ]
set AT91C_TC_CPAS [expr 0x1 << 2 ]
set AT91C_TC_CPBS [expr 0x1 << 3 ]
set AT91C_TC_CPCS [expr 0x1 << 4 ]
set AT91C_TC_LDRAS [expr 0x1 << 5 ]
set AT91C_TC_LDRBS [expr 0x1 << 6 ]
set AT91C_TC_ETRGS [expr 0x1 << 7 ]
set AT91C_TC_CLKSTA [expr 0x1 << 16 ]
set AT91C_TC_MTIOA [expr 0x1 << 17 ]
set AT91C_TC_MTIOB [expr 0x1 << 18 ]
# -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
set AT91C_TC_COVFS [expr 0x1 << 0 ]
set AT91C_TC_LOVRS [expr 0x1 << 1 ]
set AT91C_TC_CPAS [expr 0x1 << 2 ]
set AT91C_TC_CPBS [expr 0x1 << 3 ]
set AT91C_TC_CPCS [expr 0x1 << 4 ]
set AT91C_TC_LDRAS [expr 0x1 << 5 ]
set AT91C_TC_LDRBS [expr 0x1 << 6 ]
set AT91C_TC_ETRGS [expr 0x1 << 7 ]
# -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
set AT91C_TC_COVFS [expr 0x1 << 0 ]
set AT91C_TC_LOVRS [expr 0x1 << 1 ]
set AT91C_TC_CPAS [expr 0x1 << 2 ]
set AT91C_TC_CPBS [expr 0x1 << 3 ]
set AT91C_TC_CPCS [expr 0x1 << 4 ]
set AT91C_TC_LDRAS [expr 0x1 << 5 ]
set AT91C_TC_LDRBS [expr 0x1 << 6 ]
set AT91C_TC_ETRGS [expr 0x1 << 7 ]
# -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
set AT91C_TC_COVFS [expr 0x1 << 0 ]
set AT91C_TC_LOVRS [expr 0x1 << 1 ]
set AT91C_TC_CPAS [expr 0x1 << 2 ]
set AT91C_TC_CPBS [expr 0x1 << 3 ]
set AT91C_TC_CPCS [expr 0x1 << 4 ]
set AT91C_TC_LDRAS [expr 0x1 << 5 ]
set AT91C_TC_LDRBS [expr 0x1 << 6 ]
set AT?? 快捷鍵說明
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