?? at91sam7x256_inc.h
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// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity
#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase
#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer
#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer
#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer
#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer
#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer
#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer
#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer
#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer
#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer
#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer
#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer
#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate
#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK
#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Usart
// *****************************************************************************
// *** Register offset in AT91S_USART structure ***
#define US_CR ( 0) // Control Register
#define US_MR ( 4) // Mode Register
#define US_IER ( 8) // Interrupt Enable Register
#define US_IDR (12) // Interrupt Disable Register
#define US_IMR (16) // Interrupt Mask Register
#define US_CSR (20) // Channel Status Register
#define US_RHR (24) // Receiver Holding Register
#define US_THR (28) // Transmitter Holding Register
#define US_BRGR (32) // Baud Rate Generator Register
#define US_RTOR (36) // Receiver Time-out Register
#define US_TTGR (40) // Transmitter Time-guard Register
#define US_FIDI (64) // FI_DI_Ratio Register
#define US_NER (68) // Nb Errors Register
#define US_IF (76) // IRDA_FILTER Register
#define US_RPR (256) // Receive Pointer Register
#define US_RCR (260) // Receive Counter Register
#define US_TPR (264) // Transmit Pointer Register
#define US_TCR (268) // Transmit Counter Register
#define US_RNPR (272) // Receive Next Pointer Register
#define US_RNCR (276) // Receive Next Counter Register
#define US_TNPR (280) // Transmit Next Pointer Register
#define US_TNCR (284) // Transmit Next Counter Register
#define US_PTCR (288) // PDC Transfer Control Register
#define US_PTSR (292) // PDC Transfer Status Register
// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break
#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break
#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out
#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address
#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations
#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge
#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out
#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable
#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable
#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable
#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable
// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode
#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal
#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485
#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking
#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem
#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0
#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1
#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA
#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking
#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock
#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1
#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM)
#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK)
#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits
#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits
#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits
#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits
#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select
#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits
#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit
#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits
#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order
#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length
#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select
#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode
#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge
#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK
#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions
#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter
// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break
#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out
#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached
#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge
#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag
#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag
#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag
#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag
// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input
#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input
#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input
#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
// *****************************************************************************
// *** Register offset in AT91S_SSC structure ***
#define SSC_CR ( 0) // Control Register
#define SSC_CMR ( 4) // Clock Mode Register
#define SSC_RCMR (16) // Receive Clock ModeRegister
#define SSC_RFMR (20) // Receive Frame Mode Register
#define SSC_TCMR (24) // Transmit Clock Mode Register
#define SSC_TFMR (28) // Transmit Frame Mode Register
#define SSC_RHR (32) // Receive Holding Register
#define SSC_THR (36) // Transmit Holding Register
#define SSC_RSHR (48) // Receive Sync Holding Register
#define SSC_TSHR (52) // Transmit Sync Holding Register
#define SSC_SR (64) // Status Register
#define SSC_IER (68) // Interrupt Enable Register
#define SSC_IDR (72) // Interrupt Disable Register
#define SSC_IMR (76) // Interrupt Mask Register
#define SSC_RPR (256) // Receive Pointer Register
#define SSC_RCR (260) // Receive Counter Register
#define SSC_TPR (264) // Transmit Pointer Register
#define SSC_TCR (268) // Transmit Counter Register
#define SSC_RNPR (272) // Receive Next Pointer Register
#define SSC_RNCR (276) // Receive Next Counter Register
#define SSC_TNPR (280) // Transmit Next Pointer Register
#define SSC_TNCR (284) // Transmit Next Counter Register
#define SSC_PTCR (288) // PDC Transfer Control Register
#define SSC_PTSR (292) // PDC Transfer Status Register
// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable
#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable
#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable
#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable
#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset
// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection
#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock
#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal
#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin
#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
#define AT91C_SSC_CKG (0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection
#define AT91C_SSC_CKG_NONE (0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock
#define AT91C_SSC_CKG_LOW (0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low
#define AT91C_SSC_CKG_HIGH (0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High
#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection
#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start
#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input
#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input
#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input
#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input
#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input
#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input
#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0
#define AT91C_SSC_STOP (0x1 << 12) // (SSC) Receive Stop Selection
#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay
#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length
#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode
#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First
#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame
#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
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