?? 2443addr.h
字號:
//=============================================================================
// File Name : 2443addr.h
// Function : S3C2443 Define Address Register
// History
// 0.0 : Programming start (September 15,2005)
//=============================================================================
#ifndef __2443ADDR_H__
#define __2443ADDR_H__
#ifdef __cplusplus
extern "C" {
#endif
// chapter2 SYSEM CONTROLLER - jcs
#define rLOCKCON0 (*(volatile unsigned *)0x4C000000) //MPLL lock time conut
#define rLOCKCON1 (*(volatile unsigned *)0x4C000004) //EPLL lock time count
#define rOSCSET (*(volatile unsigned *)0x4C000008) //OSC stabilization control
#define rMPLLCON (*(volatile unsigned *)0x4C000010) //MPLL configuration
#define rEPLLCON (*(volatile unsigned *)0x4C000018) //EPLL configuration
#define rCLKSRC (*(volatile unsigned *)0x4C000020) //Clock source control
#define rCLKDIV0 (*(volatile unsigned *)0x4C000024) //Clock divider ratio control
#define rCLKDIV1 (*(volatile unsigned *)0x4C000028) //Clock divider ratio control
#define rHCLKCON (*(volatile unsigned *)0x4C000030) //HCLK enable
#define rPCLKCON (*(volatile unsigned *)0x4C000034) //PCLK enable
#define rSCLKCON (*(volatile unsigned *)0x4C000038) //Special clock enable
#define rPWRMODE (*(volatile unsigned *)0x4C000040) //Power mode control
#define rSWRST (*(volatile unsigned *)0x4C000044) //Software reset control
#define rBUSPRI0 (*(volatile unsigned *)0x4C000050) //Bus priority control
#define rBUSMISC (*(volatile unsigned *)0x4C000058) //Bus miscellaneous bus control
#define rSYSID (*(volatile unsigned *)0x4C00005C) //System ID control
#define rPWRCFG (*(volatile unsigned *)0x4C000060) //Power management configuration control
#define rRSTCON (*(volatile unsigned *)0x4C000064) //Reset control
#define rRSTSTAT (*(volatile unsigned *)0x4C000068) //Reset status
#define rWKUPSTAT (*(volatile unsigned *)0x4C00006c) //Wakeup status
#define rINFORM0 (*(volatile unsigned *)0x4C000070) //Sleep mode information 0
#define rINFORM1 (*(volatile unsigned *)0x4C000074) //Sleep mode information 1
#define rINFORM2 (*(volatile unsigned *)0x4C000078) //Sleep mode information 2
#define rINFORM3 (*(volatile unsigned *)0x4C00007C) //Sleep mode information 3
#define rUSB_PHYCTRL (*(volatile unsigned *)0x4C000080) //USB phy control
#define rUSB_PHYPWR (*(volatile unsigned *)0x4C000084) //USB phy power control
#define rUSB_RSTCON (*(volatile unsigned *)0x4C000088) //USB phy reset control
#define rUSB_CLKCON (*(volatile unsigned *)0x4C00008C) //USB phy clock control
#define rUSB_TESTTI (*(volatile unsigned *)0x4C000090) //USB phy test in
#define rUSB_TESTTO (*(volatile unsigned *)0x4C000094) //USB phy test out
// chapter3 EBI - oh
#define rBPRIORITY0 (*(volatile unsigned *)0x4E800000) //Matrix core 0 priority decision - edited by junon
#define rBPRIORITY1 (*(volatile unsigned *)0x4E800004) //Matrix core 1 priority decision - added by junon
#define rEBICON (*(volatile unsigned *)0x4E800008) //Bank Configuration - edited by junon
// chapter5 SSMC - junon
#define rSMBIDCYR0 (*(volatile unsigned *)0x4F000000) //Bank0 idle cycle control
#define rSMBIDCYR1 (*(volatile unsigned *)0x4F000020) //Bank1 idle cycle control
#define rSMBIDCYR2 (*(volatile unsigned *)0x4F000040) //Bank2 idle cycle control
#define rSMBIDCYR3 (*(volatile unsigned *)0x4F000060) //Bank3 idle cycle control
#define rSMBIDCYR4 (*(volatile unsigned *)0x4F000080) //Bank0 idle cycle control
#define rSMBIDCYR5 (*(volatile unsigned *)0x4F0000A0) //Bank5 idle cycle control
#define rSMBWSTRDR0 (*(volatile unsigned *)0x4F000004) //Bank0 read wait state control
#define rSMBWSTRDR1 (*(volatile unsigned *)0x4F000024) //Bank1 read wait state control
#define rSMBWSTRDR2 (*(volatile unsigned *)0x4F000044) //Bank2 read wait state control
#define rSMBWSTRDR3 (*(volatile unsigned *)0x4F000064) //Bank3 read wait state control
#define rSMBWSTRDR4 (*(volatile unsigned *)0x4F000084) //Bank4 read wait state control
#define rSMBWSTRDR5 (*(volatile unsigned *)0x4F0000A4) //Bank5 read wait state control
#define rSMBWSTWRR0 (*(volatile unsigned *)0x4F000008) //Bank0 write wait state control
#define rSMBWSTWRR1 (*(volatile unsigned *)0x4F000028) //Bank1 write wait state control
#define rSMBWSTWRR2 (*(volatile unsigned *)0x4F000048) //Bank2 write wait state control
#define rSMBWSTWRR3 (*(volatile unsigned *)0x4F000068) //Bank3 write wait state control
#define rSMBWSTWRR4 (*(volatile unsigned *)0x4F000088) //Bank4 write wait state control
#define rSMBWSTWRR5 (*(volatile unsigned *)0x4F0000A8) //Bank5 write wait state control
#define rSMBWSTOENR0 (*(volatile unsigned *)0x4F00000C) //Bank0 output enable assertion delay control
#define rSMBWSTOENR1 (*(volatile unsigned *)0x4F00002C) //Bank1 output enable assertion delay control
#define rSMBWSTOENR2 (*(volatile unsigned *)0x4F00004C) //Bank2 output enable assertion delay control
#define rSMBWSTOENR3 (*(volatile unsigned *)0x4F00006C) //Bank3 output enable assertion delay control
#define rSMBWSTOENR4 (*(volatile unsigned *)0x4F00008C) //Bank4 output enable assertion delay control
#define rSMBWSTOENR5 (*(volatile unsigned *)0x4F0000AC) //Bank5 output enable assertion delay control
#define rSMBWSTWENR0 (*(volatile unsigned *)0x4F000010) //Bank0 write enable assertion delay control
#define rSMBWSTWENR1 (*(volatile unsigned *)0x4F000030) //Bank1 write enable assertion delay control
#define rSMBWSTWENR2 (*(volatile unsigned *)0x4F000050) //Bank2 write enable assertion delay control
#define rSMBWSTWENR3 (*(volatile unsigned *)0x4F000070) //Bank3 write enable assertion delay control
#define rSMBWSTWENR4 (*(volatile unsigned *)0x4F000090) //Bank4 write enable assertion delay control
#define rSMBWSTWENR5 (*(volatile unsigned *)0x4F0000B0) //Bank5 write enable assertion delay control
#define rSMBCR0 (*(volatile unsigned *)0x4F000014) //Bank0 control
#define rSMBCR1 (*(volatile unsigned *)0x4F000034) //Bank1 control
#define rSMBCR2 (*(volatile unsigned *)0x4F000054) //Bank2 control
#define rSMBCR3 (*(volatile unsigned *)0x4F000074) //Bank3 control
#define rSMBCR4 (*(volatile unsigned *)0x4F000094) //Bank4 control
#define rSMBCR5 (*(volatile unsigned *)0x4F0000B4) //Bank5 control
#define rSMBSR0 (*(volatile unsigned *)0x4F000018) //Bank0 status
#define rSMBSR1 (*(volatile unsigned *)0x4F000038) //Bank1 status
#define rSMBSR2 (*(volatile unsigned *)0x4F000058) //Bank2 status
#define rSMBSR3 (*(volatile unsigned *)0x4F000078) //Bank3 status
#define rSMBSR4 (*(volatile unsigned *)0x4F000098) //Bank4 status
#define rSMBSR5 (*(volatile unsigned *)0x4F0000B8) //Bank5 status
#define rSMBWSTBRDR0 (*(volatile unsigned *)0x4F00001C) //Bank0 burst read wait delay control
#define rSMBWSTBRDR1 (*(volatile unsigned *)0x4F00003C) //Bank1 burst read wait delay control
#define rSMBWSTBRDR2 (*(volatile unsigned *)0x4F00005C) //Bank2 burst read wait delay control
#define rSMBWSTBRDR3 (*(volatile unsigned *)0x4F00007C) //Bank3 burst read wait delay control
#define rSMBWSTBRDR4 (*(volatile unsigned *)0x4F00009C) //Bank4 burst read wait delay control
#define rSMBWSTBRDR5 (*(volatile unsigned *)0x4F0000BC) //Bank5 burst read wait delay control
#define rSMBONETYPER (*(volatile unsigned *)0x4F000100) //OneNAND type selection - added by junon
#define rSMCSR (*(volatile unsigned *)0x4F000200) //SROMC status - edited by junon
#define rSMCCR (*(volatile unsigned *)0x4F000204) //SROMC control - edited by junon
#define SMC_REG_BASE 0x4F000000 // added by junon
#define SMC_REG_OFFSET 0x20
typedef struct tag_SMC_REGS
{
unsigned int rSmbIdCyr;
unsigned int rSmbWstRdr;
unsigned int rSmbWstWrr;
unsigned int rSmbWstOenr;
unsigned int rSmbWstWenr;
unsigned int rSmbCr;
unsigned int rSmbSr;
unsigned int rSmbWstBrdr;
} SMC_REGS;
// chapter6 MOBILE DRAM CONTROLLER - oh
#define rBANKCFG (*(volatile unsigned *)0x48000000) //Mobile DRAM configuration
#define rBANKCON1 (*(volatile unsigned *)0x48000004) //Mobile DRAM control
#define rBANKCON2 (*(volatile unsigned *)0x48000008) //Mobile DRAM timing control
#define rBANKCON3 (*(volatile unsigned *)0x4800000C) //Mobile DRAM (E)MRS
#define rREFRESH (*(volatile unsigned *)0x48000010) //Mobile DRAM refresh control
#define rTIMEOUT (*(volatile unsigned *)0x48000014) //Write Buffer Time out control
// chapter7 Nand Flash - jcs
#define rNFCONF (*(volatile unsigned *)0x4E000000) //NAND Flash configuration
#define rNFCONT (*(volatile unsigned *)0x4E000004) //NAND Flash control
#define rNFCMD (*(volatile unsigned *)0x4E000008) //NAND Flash command
#define rNFADDR (*(volatile unsigned *)0x4E00000C) //NAND Flash address
#define rNFDATA (*(volatile unsigned *)0x4E000010) //NAND Flash data
#define rNFDATA8 (*(volatile unsigned char *)0x4E000010) //NAND Flash data
#define NFDATA (0x4E000010) //NAND Flash data address
#define rNFMECCD0 (*(volatile unsigned *)0x4E000014) //NAND Flash ECC for Main
#define rNFMECCD1 (*(volatile unsigned *)0x4E000018) //NAND Flash ECC for Main
#define rNFSECCD (*(volatile unsigned *)0x4E00001C) //NAND Flash ECC for Spare Area
#define rNFSBLK (*(volatile unsigned *)0x4E000020) //NAND Flash programmable start block address
#define rNFEBLK (*(volatile unsigned *)0x4E000024) //NAND Flash programmable end block address
#define rNFSTAT (*(volatile unsigned *)0x4E000028) //NAND Flash operation status
#define rNFECCERR0 (*(volatile unsigned *)0x4E00002C) //NAND Flash ECC Error Status for I/O [7:0]
#define rNFECCERR1 (*(volatile unsigned *)0x4E000030) //NAND Flash ECC Error Status for I/O [15:8]
#define rNFMECC0 (*(volatile unsigned *)0x4E000034) //SLC or MLC NAND Flash ECC status
#define rNFMECC1 (*(volatile unsigned *)0x4E000038) //SLC or MLC NAND Flash ECC status
#define rNFSECC (*(volatile unsigned *)0x4E00003C) //NAND Flash ECC for I/O[15:0]
#define rNFMLCBITPT (*(volatile unsigned *)0x4E000040) //NAND Flash 4-bit ECC Error Pattern for data[7:0]
//chapter8 CF Interface
#define rMUX_REG (*(volatile unsigned *)0x4B801800) //Top level control & configuration register
#define rPCCARD_CFG (*(volatile unsigned *)0x4B801820) //PC card configuration & status register
#define rPCCARD_INT (*(volatile unsigned *)0x4B801824) //PC card interrupt mask & source regiseter
#define rPCCARD_ATTR (*(volatile unsigned *)0x4B801828) //PC card attribute memory area operation timing config regiseter
#define rPCCARD_IO (*(volatile unsigned *)0x4B80182C) //PC card I/O area operation timing config regiseter
#define rPCCARD_COMM (*(volatile unsigned *)0x4B801830) //PC card common memory area operation timing config regiseter
#define rATA_CON (*(volatile unsigned *)0x4B801900) //ATA_CONTROL register
#define rATA_STAT (*(volatile unsigned *)0x4B801904) //ATA_STATUS register
#define rATA_CMD (*(volatile unsigned *)0x4B801908) //ATA transfer command
#define rATA_SWRST (*(volatile unsigned *)0x4B80190C) //Software reset for the ATAPI host
#define rATA_IRQ (*(volatile unsigned *)0x4B801910) //ATA_IRQ register
#define rATA_IRQ_MASK (*(volatile unsigned *)0x4B801914) //ATA_IRQ Mask register
#define rATA_CFG (*(volatile unsigned *)0x4B801918) //ATA_CFG register
#define rATA_PIO_TIME (*(volatile unsigned *)0x4B80192C) //ATA_PIO_TIME register
#define rATA_UDMA_TIME (*(volatile unsigned *)0x4B801930) //ATA_UDMA_TIME register
#define rATA_XFR_NUM (*(volatile unsigned *)0x4B801934) //Data transfer number register
#define rATA_XFR_CNT (*(volatile unsigned *)0x4B801938) //Current remaining transfer counter
#define rATA_TBUF_START (*(volatile unsigned *)0x4B80193C) //Start address of track buffer
#define rATA_TBUF_SIZE (*(volatile unsigned *)0x4B801940) //Size of track buffer
#define rATA_SBUF_START (*(volatile unsigned *)0x4B801944) //Start address of source buffer
#define rATA_SBUF_SIZE (*(volatile unsigned *)0x4B801948) //Size of source buffer
#define rATA_CADDR_TBUR (*(volatile unsigned *)0x4B80194C) //Current address of track buffer
#define rATA_CADDR_SBUF (*(volatile unsigned *)0x4B801950) //Current address of source buffer
#define rATA_PIO_DTR (*(volatile unsigned *)0x4B801954) //16-bit PIO data register
#define rATA_PIO_FED (*(volatile unsigned *)0x4B801958) //8-bit PIO device feature/error (command block) register
#define rATA_PIO_SCR (*(volatile unsigned *)0x4B80195C) //8-bit PIO device sector count (command block) register
#define rATA_PIO_LLR (*(volatile unsigned *)0x4B801960) //8-bit PIO device LBA low (command block) register
#define rATA_PIO_LMR (*(volatile unsigned *)0x4B801964) //8-bit PIO device LBA middle (command block) register
#define rATA_PIO_LHR (*(volatile unsigned *)0x4B801968) //8-bit PIO LBA high (command block) register
#define rATA_PIO_DVR (*(volatile unsigned *)0x4B80196C) //8-bit PIO device (command block) register
#define rATA_PIO_CSD (*(volatile unsigned *)0x4B801970) //8-bit PIO device command/status (command block) register
#define rATA_PIO_DAD (*(volatile unsigned *)0x4B801974) //8-bit PIO device control/alternate status (control block) register
#define rATA_PIO_READY (*(volatile unsigned *)0x4B801978) //ATA_PIO_READY register
#define rATA_PIO_RDATA (*(volatile unsigned *)0x4B80197C) //PIO read data register while HOST read from ATA device register
#define rBUS_FIFO_STATUS (*(volatile unsigned *)0x4B801990) //BUS_FIFO_STATUS register
#define rATA_FIFO_STATUS (*(volatile unsigned *)0x4B801994) //ATA_FIFO_STATUS register
// chapter9 DMA - jcs
#define rDISRC0 (*(volatile unsigned *)0x4b000000) //DMA 0 Initial source
#define rDISRCC0 (*(volatile unsigned *)0x4b000004) //DMA 0 Initial source control
#define rDIDST0 (*(volatile unsigned *)0x4b000008) //DMA 0 Initial Destination
#define rDIDSTC0 (*(volatile unsigned *)0x4b00000c) //DMA 0 Initial Destination control
#define rDCON0 (*(volatile unsigned *)0x4b000010) //DMA 0 Control
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