MCASP_ConfigSrctl srctlRegs =
     {
          MCASP_SRCTL_RMK(
               MCASP_SRCTL_DISMOD_LOW,
               MCASP_SRCTL_SRMOD_XMT),  /* SRCTL0 */
          MCASP_SRCTL_RMK(
               MCASP_SRCTL_DISMOD_LOW,
               MCASP_SRCTL_SRMOD_RCV),  /* SRCTL1 */
          MCASP_SRCTL_RMK(
               MCASP_SRCTL_DISMOD_LOW,
               MCASP_SRCTL_SRMOD_XMT),  /* SRCTL2 */
          MCASP_SRCTL_RMK(
               MCASP_SRCTL_DISMOD_LOW,
               MCASP_SRCTL_SRMOD_RCV),  /* SRCTL3 */
          MCASP_SRCTL_RMK(
               MCASP_SRCTL_DISMOD_LOW,
               MCASP_SRCTL_SRMOD_XMT),  /* SRCTL4 */
          MCASP_SRCTL_RMK(
               MCASP_SRCTL_DISMOD_LOW,
               MCASP_SRCTL_SRMOD_RCV),  /* SRCTL5 */
          MCASP_SRCTL_RMK(
               MCASP_SRCTL_DISMOD_LOW,
               MCASP_SRCTL_SRMOD_XMT),  /* SRCTL6 */
          MCASP_SRCTL_RMK(
               MCASP_SRCTL_DISMOD_LOW,
               MCASP_SRCTL_SRMOD_RCV),  /* SRCTL7 */
     }; 

     MCASP_ConfigGbl globalRegs =
     {
          MCASP_PFUNC_RMK(
               MCASP_PFUNC_AFSR_MCASP,
               MCASP_PFUNC_AHCLKR_MCASP,
               MCASP_PFUNC_ACLKR_MCASP,
               MCASP_PFUNC_AFSX_MCASP,
               MCASP_PFUNC_AHCLKX_MCASP,
               MCASP_PFUNC_ACLKX_MCASP,
               MCASP_PFUNC_AMUTE_DEFAULT,
               MCASP_PFUNC_AXR7_MCASP,
               MCASP_PFUNC_AXR6_MCASP,
               MCASP_PFUNC_AXR5_MCASP,
               MCASP_PFUNC_AXR4_MCASP,
               MCASP_PFUNC_AXR3_MCASP,              
               MCASP_PFUNC_AXR2_MCASP,              
               MCASP_PFUNC_AXR1_MCASP,              
               MCASP_PFUNC_AXR0_MCASP),              
          MCASP_PDIR_RMK(
               MCASP_PDIR_AFSR_OUT,
               MCASP_PDIR_AHCLKR_OUT,
               MCASP_PDIR_ACLKR_OUT,
               MCASP_PDIR_AFSX_OUT,
               MCASP_PDIR_AHCLKX_OUT,
               MCASP_PDIR_ACLKX_OUT,               
               MCASP_PDIR_AMUTE_DEFAULT,
               MCASP_PDIR_AXR7_IN,
               MCASP_PDIR_AXR6_OUT,             
               MCASP_PDIR_AXR5_IN,             
               MCASP_PDIR_AXR4_OUT,             
               MCASP_PDIR_AXR3_IN,             
               MCASP_PDIR_AXR2_OUT,             
               MCASP_PDIR_AXR1_IN,             
               MCASP_PDIR_AXR0_OUT),                       
          MCASP_DITCTL_DEFAULT,
          MCASP_DLBCTL_RMK(
               MCASP_DLBCTL_MODE_XMTCLK, 
               MCASP_DLBCTL_ORD_XMTEVEN, 
               MCASP_DLBCTL_DLBEN_ENABLE),
          MCASP_AMUTE_DEFAULT     
     }; 

     /*---------------------------------------------------------------*/
     /* 2. Configure all registers except GBLCTL                      */
     /*---------------------------------------------------------------*/  
     // Step 2a: Leave PWRDEMU at default.
     
     // Step 2b: Receiver registers
     
    clkSetup.syncmode = MCASP_ACLKXCTL_ASYNC_ASYNC;
    clkSetup.xclkdiv = MCASP_ACLKXCTL_CLKXDIV_OF(0xA);
    clkSetup.xclkpol = MCASP_ACLKXCTL_CLKXP_RISING;
    clkSetup.xclksrc = MCASP_ACLKXCTL_CLKXM_INTERNAL;

    
    clkSetup.rclkdiv = MCASP_ACLKRCTL_CLKRDIV_OF(0xB);
    clkSetup.rclkpol = MCASP_ACLKRCTL_CLKRP_FALLING;
    clkSetup.rclksrc = MCASP_ACLKRCTL_CLKRM_INTERNAL;
    
    MCASP_setupClk (hMcasp, &clkSetup, MCASP_RCV);
    
    clkSetup.xclkdiv = MCASP_ACLKXCTL_CLKXDIV_OF(0x12);
    clkSetup.xclkpol = MCASP_ACLKXCTL_CLKXP_FALLING;
    clkSetup.xclksrc = MCASP_ACLKXCTL_CLKXM_INTERNAL;
    MCASP_setupClk (hMcasp, &clkSetup, MCASP_XMT);
     
     
     
    hClkSetup.rhclkdiv = MCASP_AHCLKRCTL_HCLKRDIV_OF(0xFFF);
    hClkSetup.rhclkpol = MCASP_AHCLKRCTL_HCLKRP_FALLING;
    hClkSetup.rhclksrc = MCASP_AHCLKRCTL_HCLKRM_INTERNAL;
    hClkSetup.xhclkdiv = MCASP_AHCLKXCTL_HCLKXDIV_OF(0xF01);    
    hClkSetup.xhclkpol = MCASP_AHCLKXCTL_HCLKXP_FALLING;
    hClkSetup.xhclksrc = MCASP_AHCLKXCTL_HCLKXM_INTERNAL;
    
    MCASP_setupHclk (hMcasp, &hClkSetup, MCASP_XMTRCV);    
     
    hClkSetup.rhclkdiv = MCASP_AHCLKRCTL_HCLKRDIV_OF(0x020);
    hClkSetup.rhclkpol = MCASP_AHCLKRCTL_HCLKRP_RISING;
    hClkSetup.rhclksrc = MCASP_AHCLKRCTL_HCLKRM_INTERNAL;    
    
    MCASP_setupHclk (hMcasp, &hClkSetup, MCASP_RCV); 
    
    hClkSetup.xhclkdiv = MCASP_AHCLKXCTL_HCLKXDIV_OF(0x04E);    
    hClkSetup.xhclkpol = MCASP_AHCLKXCTL_HCLKXP_RISING;
    hClkSetup.xhclksrc = MCASP_AHCLKXCTL_HCLKXM_INTERNAL;
    MCASP_setupHclk (hMcasp, &hClkSetup, MCASP_XMT);
     
    
    fsyncSetup.rmode = MCASP_AFSRCTL_RMOD_BURST;
    
    fsyncSetup.frwid = MCASP_AFSRCTL_FRWID_BIT;
    fsyncSetup.rfspol = MCASP_AFSRCTL_FSRP_ACTIVEHIGH;
    fsyncSetup.rfssrc = MCASP_AFSRCTL_FSRM_INTERNAL;
    fsyncSetup.rslotsize = MCASP_AFSRCTL_RMOD_OF(0x10);
    fsyncSetup.rmode = 1;
    fsyncSetup.fxwid = MCASP_AFSXCTL_FXWID_BIT;
    fsyncSetup.xfspol = MCASP_AFSXCTL_FSXP_ACTIVEHIGH;
    fsyncSetup.xfssrc = MCASP_AFSXCTL_FSXM_INTERNAL;
    fsyncSetup.xslotsize = MCASP_AFSXCTL_XMOD_OF(0x1F);
    fsyncSetup.xmode = 1;
    
    MCASP_setupFsync (hMcasp, &fsyncSetup, MCASP_XMTRCV);  
    
    fsyncSetup.frwid = MCASP_AFSRCTL_FRWID_WORD;
    fsyncSetup.rfspol = MCASP_AFSRCTL_FSRP_ACTIVELOW;
    fsyncSetup.rfssrc = MCASP_AFSRCTL_FSRM_INTERNAL;
    fsyncSetup.rslotsize = MCASP_AFSRCTL_RMOD_OF(0x10F);
    fsyncSetup.rmode = 1;
    
    MCASP_setupFsync (hMcasp, &fsyncSetup, MCASP_RCV);    

    fsyncSetup.fxwid = MCASP_AFSXCTL_FXWID_WORD;
    fsyncSetup.xfspol = MCASP_AFSXCTL_FSXP_ACTIVELOW;
    fsyncSetup.xfssrc = MCASP_AFSXCTL_FSXM_INTERNAL;
    fsyncSetup.xslotsize = MCASP_AFSXCTL_XMOD_OF(0x1FF);
    fsyncSetup.xmode = 1;
    MCASP_setupFsync (hMcasp, &fsyncSetup, MCASP_XMT); 
    

    formatSetup.ralign = MCASP_FORMAT_RIGHT;
    formatSetup.rbusel = MCASP_RFMT_RBUSEL_CFG;
    formatSetup.rdelay = MCASP_RFMT_RDATDLY_2BIT;
    formatSetup.rdsprep = MCASP_DSP_Q31;
    formatSetup.rorder = MCASP_FORMAT_MSB;
    formatSetup.rslotsize = 24;
    formatSetup.rwordsize = 20;
    formatSetup.rpad = MCASP_RFMT_RPAD_RPBIT;
    formatSetup.rpbit = MCASP_RFMT_RPBIT_OF(1);
    
    formatSetup.xalign = MCASP_FORMAT_RIGHT;
    formatSetup.xbusel = MCASP_XFMT_XBUSEL_DAT;
    formatSetup.xdelay = MCASP_XFMT_XDATDLY_1BIT;
    formatSetup.xdsprep = MCASP_DSP_Q31;
    formatSetup.xorder = MCASP_FORMAT_MSB;
    formatSetup.xslotsize = 32;
    formatSetup.xwordsize = 16;
    formatSetup.xpad = MCASP_XFMT_XPAD_XPBIT;
    formatSetup.xpbit = MCASP_XFMT_XPBIT_OF(2);
    
    MCASP_setupFormat(hMcasp, &formatSetup, MCASP_XMTRCV);
     
    
    // Set up DIT transmission for Q31 24-bit data type  
    
    MCASP_configDit(hMcasp,(MCASP_Dsprep)1,24); 

	 
	MCASP_configRcv(hMcasp, &rcvRegs);  
	 
	// Step 2c: Transmitter registers
	MCASP_configXmt(hMcasp, &xmtRegs);        	 

    // Step 2d: Serializer registers
	MCASP_configSrctl(hMcasp, &srctlRegs);  
	 
	// Step 2e: PFUNC, PDIR, DITCTL, DLBCTL, AMUTE.
	MCASP_configGbl(hMcasp, &globalRegs);   
     
     
    /*---------------------------------------------------------------*/
    /* 3. Start Serial Clocks                                        */
    /*---------------------------------------------------------------*/  
     
    // Step 3a: Take clk dividers out of reset
    // Step 3b: Read back GBLCTL to make sure the clock resets are written to errorfully          
     
    MCASP_enableHclk(hMcasp, MCASP_XMTRCV);
    while(!(  MCASP_FGETH(hMcasp, GBLCTL,XHCLKRST)));
     
    MCASP_enableClk(hMcasp, MCASP_XMTRCV);
    while(!(  MCASP_FGETH(hMcasp, GBLCTL,XCLKRST)));

     
} /* end of InitMcasp() */




/************************************************************************\
 name:      WakeRcvXmt

 purpose:   Wake up the Receiver by taking serializer and state machine
            out of reset. 
            Wake up the transmitter by:
            1. taking serializer out of reset
            2. verifying that all transmit buffers are serviced
            3. taking state machine out of reset.
            Note that every time the GBLCTL register is written to,
            it must be read back to ensure it was written errorfully.            

 inputs:    int port            : McASP port #

 returns:   n/a
\************************************************************************/
void WakeRcvXmt(int port)
{
     
     /*---------------------------------------------------------------*/
     /* Take serializer out of reset                                  */
     /* Both transmit and receive                                     */
     /*---------------------------------------------------------------*/       

     MCASP_enableSers(hMcasp, MCASP_RCVXMT);
     while(!(MCASP_FGETH(hMcasp,GBLCTL,RSRCLR) & MCASP_FGETH(hMcasp,GBLCTL,XSRCLR)));

     /*---------------------------------------------------------------*/
     /* Verify all transmit buffers are serviced                      */
     /*---------------------------------------------------------------*/  

     while(MCASP_FGETH(hMcasp,XSTAT,XDATA));

     /*---------------------------------------------------------------*/
     /* Take transmit and receive state machine out of reset          */
     /*---------------------------------------------------------------*/       

     MCASP_enableSm(hMcasp, MCASP_RCVXMT);
     while(!(MCASP_FGETH(hMcasp,GBLCTL,RSMRST) & MCASP_FGETH(hMcasp,GBLCTL,XSMRST)));
     
}