?? instruction.asm
字號:
;*******************************************************************************
; FILENAME : Instruction.ASM
; AUTHOR : SONiX
; PURPOSE : Test Instruction function which defined by SONiX
; REVISION : 28/01/2003 V1.0 First issue
;*******************************************************************************
;* (c) Copyright 2002, SONiX TECHNOLOGY CO., LTD.
;*******************************************************************************
CHIP SN8P1708 ; Select the CHIP
//{{SONIX_CODE_OPTION
.Code_Option OSG Enable
.Code_Option High_Clk 4M_X'tal
.Code_Option High_Clk/2 Disable
.Code_Option Security Enable
.Code_Option LVD Enable
.Code_Option Watch_Dog Disable
//}}SONIX_CODE_OPTION
;-------------------------------------------------------------------------------
; Include Files
;-------------------------------------------------------------------------------
.nolist ; do not list the macro file
INCLUDESTD MACRO1.H
INCLUDESTD MACRO2.H
INCLUDESTD MACRO3.H
.list ; Enable the listing function
;-------------------------------------------------------------------------------
; Constants Definition
;-------------------------------------------------------------------------------
; ONE EQU 1
;-------------------------------------------------------------------------------
; xyz_a and inc_xyz macro
;-------------------------------------------------------------------------------
xyz_a macro
add z,a ; z = z + a
b0bts1 FC ; Is carry = 1
jmp @f ; no carry
incms y ; carry = 1 --> y ++
jmp @f
incms x
nop
@@:
endm
inc_xyz macro
incms z ; Z ++
jmp @f ; not overflow
incms y ; Y ++
jmp @f ; not overflow
incms x ; X ++
nop
@@:
endm
;-------------------------------------------------------------------------------
; Variables Definition
;-------------------------------------------------------------------------------
.DATA
org 0h ;Bank 0 data section start from RAM address 0x000
Wk00B0 DS 1 ;Temporary buffer for main loop
Iwk00B0 DS 1 ;Temporary buffer for ISR
AccBuf DS 1 ;Accumulater buffer
PflagBuf DS 1 ;PFLAG buffer
wk00 DS 1 ; Ram
wk01 DS 1 ; Ram
wk02 DS 1 ; Ram
wk03 DS 1 ; Ram
org 100h ;Bank 1 data section start from RAM address 0x100
BufB1 DS 20 ;Temporary buffer in bank 1
;-------------------------------------------------------------------------------
; Bit Flag Definition
;-------------------------------------------------------------------------------
Wk00B0_0 EQU Wk00B0.0 ;Bit 0 of Wk00B0
Iwk00B0_1 EQU Iwk00B0.1 ;Bit 1 of Iwk00
;-------------------------------------------------------------------------------
; Code section
;-------------------------------------------------------------------------------
.CODE
ORG 0 ;Code section start
jmp Reset ;Reset vector
;Address 4 to 7 are reserved
ORG 8
jmp Isr ;Interrupt vector
ORG 10h
;-------------------------------------------------------------------------------
; Program reset section
;-------------------------------------------------------------------------------
Reset:
mov A,#07Fh ;Initial stack pointer and
b0mov STKP,A ;disable global interrupt
b0mov PFLAG,#00h ;pflag = x,x,x,x,x,c,dc,z
b0mov RBANK,#00h ;Set initial RAM bank in bank 0
mov A,#40h ;Clear watchdog timer and initial system mode
b0mov OSCM,A
call ClrRAM ;Clear RAM
call SysInit ;System initial
b0bset FGIE ;Enable global interrupt
;-------------------------------------------------------------------------------
; Main routine
;-------------------------------------------------------------------------------
Main:
b0bset FWDRST ;Clear watchdog timer
call MnApp
jmp Main
;-------------------------------------------------------------------------------
; Main application
;-------------------------------------------------------------------------------
MnApp:
; Put your main program here
;*******************************************************************************
; Sonix Instruction Manual
;*******************************************************************************
;
; Mov a,i
;
mov a,#0xff
mov a,#55h
mov a,#55
mov a,#10101010b
;
; Mov M,a
;
mov a,#100
b0mov wk00,a
mov a,#00
b0mov wk00,a ; Z = 1
mov a,#0xaa
b0mov wk00,a
;
; mov a,m
;
mov a,#00
b0mov a,wk00
;
;*******************************************************************************
; Only H,L,R,X,Y,Z,Pflag,Rbank
;*******************************************************************************
;
; b0mov m,I
;
b0mov h,#55h ;
b0mov l,#0xaa
b0mov r,#0xff
b0mov x,#1
b0mov y,#2
b0mov z,#4
;*******************************************************************************
;
; xch a,m
;
b0xch a,h
b0xch a,l
b0xch a,wk00
;*******************************************************************************
;
; add a,m
;
mov a,#40h
b0mov wk00,a
mov a,#0
add a,wk00
add a,wk00
add a,wk00
add a,wk00
add a,wk00
;
; add m,a
;
mov a,#00
b0mov wk00,a
mov a,#40h
add wk00,a
add wk00,a
add wk00,a
add wk00,a
add wk00,a
;
; adc a,m
;
mov a,#40h
b0mov wk00,a
mov a,#0
adc a,wk00
adc a,wk00
adc a,wk00
adc a,wk00
adc a,wk00
;
; adc m,a
;
mov a,#00
b0mov wk00,a
mov a,#40h
adc wk00,a
adc wk00,a
adc wk00,a
adc wk00,a
adc wk00,a
;*******************************************************************************
;
; 16 bits ADD
; wk03,wk02 = wk03,wk02 + wk01,wk00
;
B0BCLR FC ; Check the Carry bit location in the sn8asm
B0BSET FC ;
B0BCLR FC ;
mov a,#0x34
b0mov wk01,a
mov a,#0x56
b0mov wk00,a ; 0x3456
mov a,#0x78
b0mov wk03,a
mov a,#0x9a
b0mov wk02,a ; 0x789a
;
; Low Byte
;
b0mov a,wk00
add wk02,a
;
; Hi byte
;
b0mov a,wk01
adc wk03,a ; 0xACF0
;
; Low Byte
;
b0mov a,wk00
add wk02,a
;
; Hi byte
;
b0mov a,wk01
adc wk03,a ; 0xE146
;
;*******************************************************************************
; Test the Sub
;*******************************************************************************
;
; SUB and SBC
;
b0mov a,wk02 ; 0xE146-0x3456 --> 0xACF0
sub a,wk00
b0mov wk02,a ; C = 0
b0mov a,wk03
sbc a,wk01 ; A-WK01-not_C --> 0xE1-0x34-1 --> 0xAC
b0mov wk03,a ; C = 1
;
; SUB and SBC
;
b0mov a,wk02 ; 0xACF0-0x3456 --> 0x789A
sub a,wk00
b0mov wk02,a ; C = 1
b0mov a,wk03
sbc a,wk01 ; 0xAC-0x34 - 0 --> 0x78
b0mov wk03,a ; C = 1
;*******************************************************************************
;
; DAA
;
mov a,#9h
b0mov wk00,a
add a,wk00
daa
b0mov wk00,a ; 18 = 9 + 9
add a,wk00
daa
b0mov wk00,a ; 36 = 18 + 18
add a,wk00
daa
b0mov wk00,a ; 72 = 36 +36
add a,wk00
daa
b0mov wk00,a ; C= 1, 44 = 72+72
add a,wk00
daa
b0mov wk00,a ; 88 = 44 + 44
add a,wk00
daa
b0mov wk00,a ; c=1,76=88+88
;*******************************************************************************
;
; Logical AND
;
mov a,#0xaa ; a=0xaa
b0mov wk00,a ; wk00=0xaa
;
; and a,m
;
and a,wk00 ; a = 0xaa
;
; And a,I
;
and a,#0xf0 ; a = 0xa0
;
; And m,a
;
mov a,#0x0f ; a = 0x0f
and wk00,a ; wk00 = 0x0a
;*******************************************************************************
;
; Logical OR
;
mov a,#0xaa ; a=0xaa
b0mov wk00,a ; wk00=0xaa
mov a,#0xf0 ; a= 0xf0
;
; OR a,m
;
OR a,wk00 ; a= 0xfa
;
; OR a,I
;
OR a,#0x0f ; a= 0xff
;
; OR m,a
;
mov a,#0x0f ; a = 0x0f
OR wk00,a ; wk00 = 0xaf
;*******************************************************************************
;
; Logical XOR
;
mov a,#0xaa ; a = 0xaa
b0mov wk00,a ; wk00 = 0xaa
;
; xor a,m
;
mov a,#0xff ;
xor a,wk00 ; a = 0x55
;
; Xor a,M
;
mov a,#0x00 ; a = 0
xor a,wk00 ; a = 0xaa
;
; Xor a,I
;
mov a,#0x55 ; a = 0x55
xor a,#0xff ; a = 0xaa
;
; Xor M,A
;
mov a,#0xff ; a = 0xff
xor wk00,a ; wk00 = 0x55
;*******************************************************************************
;
; SWAP
;
mov a,#0xa5 ; a = 0xa5
b0mov wk00,a ; wk00 = 0xa5
mov a,#00 ; a = 0
swap wk00 ; a = 0x5a , but wk00 = 0xa5
;*******************************************************************************
;
; SWAPM
;
swapm wk00 ; wk00 = 0x5a
;*******************************************************************************
;
; RRC
;
b0bclr FC
mov a,#0x80
b0mov wk00,a ; wk00 = 0x80
rrcm wk00 ; 1 --> wk00 = 0x40
rrcm wk00 ; 2
rrcm wk00 ; 3
rrcm wk00 ; 4
rrcm wk00 ; 5
rrcm wk00 ; 6
rrcm wk00 ; 7
rrcm wk00 ; 8
rrcm wk00 ; 9 --> wk00 = 0x80 again !
b0bclr FC
mov a,#0x85 ; a = 0x85
b0mov wk00,a ; wk00 = 0x85
rrc wk00 ; a = 0x42, wk00=0x85
rrc wk00 ; a = 0x42, wk00=0x85 , C=1
rrcm wk00 ; wk00 = 0xC2 , C=1
rrcm wk00 ; wk00 = 0xE1 , C=0
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