; == IDENTIFICATION ================================================== */ 
;

;
; == HISTORY ========================================================= */ 
;                                                                         
; Name         Date       Ver  Action                                    
; -------------------------------------------------------------------- 
; tcmc_ore    10-Aug-04    4   Always map cbm10 and 11
; tcmc_ore    22-Jul-04    3   Only reserve 240 bytes for BMP var's
; tcmc_ore    21-Jul-04    2   Restrict available RAM to 36kB (0x9000)
; tcmc_ore    19-Apr-04    1   Creation: VegaBB memory map


; --------------------------------------------------------------------
; Specify instruction memory (IMEM) area
; --------------------------------------------------------------------

IMEM     0x00000000 0x000E0000  ; 896k of IMEM (ROM/FLASH)
{
    IMEM 0x00000000
    {
      ssw01fiq.o(Startup, +First)	
      * (+RO)
    }

    ;---------------------------------------------------------------------
    ; Specify ARM System Bus (ASB) Region for 36k of SRAM @ 16M
    ; to be located after the IMEM in the image for reevaluation
    ; of global initializers by startup.s
    ; These 36k include: 0.6k reserved for BMP Driver (in VegaTB ROM)
    ;                    1.0k allocated for stack (in startup.s) and 
    ;
    ; Note that this requires the whole RAM to be zeroed at startup time
    ;---------------------------------------------------------------------
    SCT  0x01000240
    {
       *lm11dat.o (+ZI); SCTs must be within first 16kB => place to start of RAM
    } 

    SRAM +0
    {
       cbm*.o
       * (+RW, +ZI)
        startup.o (DummyStack, +Last)
    }

    JUSTAFTERRAM 0x1009000
    {
	startup.o (JustAfterRAM)
    }
}


;---------------------------------------------------------------------
; Specify ARM System Bus (ASB) region for peripheral blocks 
; (SCU, ICU, DRT)
;---------------------------------------------------------------------

SCU      0x0111D800
{
    SCU  0x0111D800
    {
        csys1scu.o(+ZI)
    }
}

ICU      0x0111DA00
{
    ICU  0x0111DA00
    {
        csys1icu.o(+ZI)
    }
}

DRT      0x01116000
{
    DRT  0x01116000
    {
        csys1drt.o(+ZI)
    }
}


;---------------------------------------------------------------------
; Specify ASB region for BMP Registers and Control Unit Arrays
;--------------------------------------------------------------------- 

BMPReg     0x0111A000
{
    BMPReg 0x0111A000
    {
        cbm10hwr.o (+ZI) ; Place BMP registers in this area
    }
}

XCUCom      0x0111B000
{
     XCUCom 0x0111B000 
     {
         cbm11hwa.o (+ZI) ; Place BMP arrays in this area
     }
}


;---------------------------------------------------------------------
; Specify ASB region for VLSI Peripheral Bus (VPB)
;---------------------------------------------------------------------

SPI       0x0111C000
{
    SPI   0x0111C000 
    {
        csys3spi.o (+ZI) ; 
    }
}
IIC       0x0111C200
{
    IIC   0x0111C200 
    {
        csys3iic.o (+ZI) ; 
    }
}
KBS       0x0111C400 
{
    KBS   0x0111C400 
    {
        csys3kbs.o (+ZI) ; 
    }
}
GPIO      0x0111C600 
{
    GPIO  0x0111C600 
    {
        csys3gio.o (+ZI) ; 
    }
}
TIM       0x0111C800 
{
    TIM   0x0111C800 
    {
        csys3tim.o (+ZI) ; 
    }
}
BIF       0x0111CA00 
{
    BIF   0x0111CA00 
    {
        csys3bif.o (+ZI) ; 
    }
}
DAIF      0x0111CC00 
{
    DAIF  0x0111CC00 
    {
        csys3dai.o (+ZI) ; 
    }
}
IPINT     0x0111CE00 
{
    IPINT 0x0111CE00 
    {
        csys3ipi.o (+ZI) ; 
    }
}
UART      0x0111D000 
{
    UART  0x0111D000 
    {
        csys3uax.o (+ZI) ; 
    }
}
PAO       0x0111D200 
{
    PAO   0x0111D200 
    {
        csys3pao.o (+ZI) ; 
    }
}
ADPCM	  0x0111D400
{
     ADPCM 0x0111D400
     {
	csys3adp.o (+ZI) ; 
     }
}
DFAC      0x0111DC00 
{
    DFAC   0x0111DC00 
    {
        csys3dfa.o (+ZI) ; 
    }
}

SDC0      0x0111DE00 
{
    SDC0  0x0111DE00 
    {
        csys3sd0.o (+ZI) ; 
    }
}
SDC1      0x0111DE80 
{
    SDC1  0x0111DE80 
    {
        csys3sd1.o (+ZI) ; 
    }
}
SDC2      0x0111DF00 
{
    SDC2  0x0111DF00 
    {
        csys3sd2.o (+ZI) ; 
    }
}
SDC3      0x0111DF80 
{
    SDC3  0x0111DF80 
    {
        csys3sd3.o (+ZI) ; 
    }
}

SDC4      0x0111E000 
{
    SDC4  0x0111E000 
    {
        csys3sd4.o (+ZI) ; 
    }
}

;---------------------------------------------------------------------
; Mailbox Unit areas (DSP): addresses are provided in DSP header file
;---------------------------------------------------------------------

MUR          0x01180000
{
    MUR      0x01180000 
    {
        csys7mur.o (+ZI) ; 
    }
}
DSPIO        0x01190000
{
    DSPIO    0x01190000 
    {
        csys7dio.o (+ZI) ; 
    }
}
DSP_XMEM     0x011A0000
{
    DSP_XMEM 0x011A0000 
    {
        csys7dxm.o (+ZI) ; 
    }
}
DSP_YMEM     0x011C0000 
{
    DSP_YMEM 0x011C0000 
    {
        csys7dym.o (+ZI) ; 
    }
}
DSP_PMEM     0x011E0000 
{
    DSP_PMEM 0x011E0000 
    {
        csys7dpm.o (+ZI) ; 
    }
}
;---------------------------------------------------------------------
; End of region specifications
;---------------------------------------------------------------------


;; !!!!!!!!!!!!!!! THIS SECTION IS NOT YET UPDATED FOR VEGA-TB !!!!!!!!!!!!!!!!!!!
;;
;; explanation of apiarmul.mem (here, because armsd does not accept comments there)
;; 
;; apiarmul.mem
;; ============
;; The format of each line is:
;;     start size name width access read-times write-times
;; 
;; start   
;;     is the start address of the memory region in hexadecimal, for example, 80000.
;; size    
;;     is the size of the memory region in hexadecimal, for example, 4000.
;; name    
;;     is a single word that you can use to identify the memory region when
;;     memory access statistics are displayed. You can use any name. To ease
;;     readability of the memory access statistics, give a descriptive name such
;;     as SRAM, DRAM, or EPROM.
;;     width is the width of the data bus in bytes (that is, 1 for an 8-bit bus, 2 for a
;;     16-bit bus, or 4 for a 32-bit bus).
;; access  
;;     describes the type of access that may be performed on this region of memory:
;;         r   for read-only.
;;         w   for write-only.
;;         rw  for read-write.
;;         -   for no access.
;;     An asterisk (*) may be appended to the access to describe a Thumb-based
;;     system that uses a 32-bit data bus, but which has a 16-bit latch to latch the
;;     upper 16 bits of data, so that a subsequent 16-bit sequential access can be
;;     fetched directly out of the latch.
;; read-times
;;     describes the nonsequential and sequential read times in nanoseconds.
;;     These should be entered as the nonsequential read access time followed
;;     by / (slash), followed by the sequential read access time. Omitting the /
;;     and using only one figure indicates that the nonsequential and sequential
;;     access times are the same.
;;     Note:
;;         Do not simply enter the times quoted on top of a memory chip. You must
;;         add a 20-30ns signal propagation time to them.
;; write-times
;;     describes the nonsequential and sequential write times. The format is
;;     identical to that of read times.
;;     
;; PCD801X: PT 14MHz, FT28MHz => no wait states except APB  (1ws)
;;          time[ns] based upon 1MHz clock setting  
;; 
;; start       size        name width access  readN/S  writeN/S
;; 00000000    0003FC00    IMEM    4   R          1/1       1/1
;; 01000000    00002000    SRAM    4   RW         1/1       1/1
;; 01114000    00006000    SYS     4   RW         1/1       1/1
;; 0111A000    00002000    BMP     4   RW         1/1       1/1
;; 0111C000    00002000    APB     4   RW      1001/1001 1001/1001
;; 01180000    00080000    DSP     4   RW      5001/5001    1/5001

;eof