JDF G
// Created by Project Navigator ver 1.0
PROJECT clock
DESIGN clock
DEVFAM spartan3
DEVFAMTIME 0
DEVICE xc3s200
DEVICETIME 0
DEVPKG ft256
DEVPKGTIME 0
DEVSPEED -4
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 1077650443
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE clock.vhd
DEPASSOC clock clock.ucf
[STRATEGY-LIST]
Normal=True