library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;              

entity chen is
 port(
    in1: in std_logic_vector(3 downto 0); 
    in2: in std_logic_vector(3 downto 0);  
    out: out std_logic_vector(7 downto 0);
    );
end chen;

architecture behave of chen is
begin 
process()
  begin
     case in1 is
        when "0000"=>
             data<="0000";          
        when "0001"=>     
             data<=in2;
        when "0010"=>   
             data<=in2<<2; 
        when "0011"=>  
          case in2 is
             when "0000"=> data<="0000"; 
             when "0001"=> data<="0011"; 
             when "0010"=> data<="0000"; 
             when "0001"=> data<="0011"; 
             when "0000"=> data<="0000"; 
             when "0001"=> data<="0011"; 
             when "0000"=> data<="0000"; 
             when "0001"=> data<="0011"; 
             when "0000"=> data<="0000"; 
             when "0001"=> data<="0011"; 
             
             when others=> data<="ZZZZ"; int0<='1';
           end case;
        end case;
end process;
end behave;