module mainctrl( clk, PhaseM,Div,phase,cs,fc,clk_kb);
input clk;
input[10:0] PhaseM;
input[4:0] Div;
output cs,clk_kb,fc;
output[7:0] phase;

reg[4:0]  	devider;
reg[15:0] 	counter;
reg[3:0]	cnt;

reg 		fc;

always @(posedge clk)
  begin
	devider=devider+1;
	if (devider==Div)
		begin 
			fc=~fc;
			devider=0;
		end
  end

always @(posedge clk)
	begin
		cnt=cnt+1;
	end

always @(posedge fc)
  begin
	counter=counter+PhaseM;
  end

assign phase[7:0]=counter[15:8];
assign cs=cnt[2];
assign clk_kb=cnt[3];
endmodule