?? tte.rpt
字號:
& = Uses single-pin Output Enable
Device-Specific Information: e:\mydds\verilog\tte.rpt
tte
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 8 - C 14 LCELL s 1 0 1 0 b0~1
- 7 - A 07 LCELL s 1 0 1 0 b1~1
- 7 - B 15 LCELL s 1 0 1 0 b2~1
- 8 - C 08 LCELL s 1 0 1 0 b3~1
- 5 - A 03 LCELL s 1 0 1 0 b4~1
- 1 - B 17 LCELL s 1 0 1 0 b5~1
- 4 - C 15 LCELL s 1 0 1 0 b6~1
- 2 - B 03 LCELL s 1 0 1 0 b7~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\mydds\verilog\tte.rpt
tte
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 2/ 48( 4%) 0/ 48( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
B: 2/ 96( 2%) 0/ 48( 0%) 2/ 48( 4%) 1/16( 6%) 3/16( 18%) 0/16( 0%)
C: 1/ 96( 1%) 1/ 48( 2%) 2/ 48( 4%) 1/16( 6%) 3/16( 18%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\mydds\verilog\tte.rpt
tte
** EQUATIONS **
a0 : INPUT;
a1 : INPUT;
a2 : INPUT;
a3 : INPUT;
a4 : INPUT;
a5 : INPUT;
a6 : INPUT;
a7 : INPUT;
-- Node name is 'b0~1'
-- Equation name is 'b0~1', location is LC8_C14, type is buried.
-- synthesized logic cell
_LC8_C14 = LCELL( a0);
-- Node name is 'b0'
-- Equation name is 'b0', type is output
b0 = !_LC8_C14;
-- Node name is 'b1~1'
-- Equation name is 'b1~1', location is LC7_A7, type is buried.
-- synthesized logic cell
_LC7_A7 = LCELL( a1);
-- Node name is 'b1'
-- Equation name is 'b1', type is output
b1 = !_LC7_A7;
-- Node name is 'b2~1'
-- Equation name is 'b2~1', location is LC7_B15, type is buried.
-- synthesized logic cell
_LC7_B15 = LCELL( a2);
-- Node name is 'b2'
-- Equation name is 'b2', type is output
b2 = !_LC7_B15;
-- Node name is 'b3~1'
-- Equation name is 'b3~1', location is LC8_C8, type is buried.
-- synthesized logic cell
_LC8_C8 = LCELL( a3);
-- Node name is 'b3'
-- Equation name is 'b3', type is output
b3 = !_LC8_C8;
-- Node name is 'b4~1'
-- Equation name is 'b4~1', location is LC5_A3, type is buried.
-- synthesized logic cell
_LC5_A3 = LCELL( a4);
-- Node name is 'b4'
-- Equation name is 'b4', type is output
b4 = !_LC5_A3;
-- Node name is 'b5~1'
-- Equation name is 'b5~1', location is LC1_B17, type is buried.
-- synthesized logic cell
_LC1_B17 = LCELL( a5);
-- Node name is 'b5'
-- Equation name is 'b5', type is output
b5 = !_LC1_B17;
-- Node name is 'b6~1'
-- Equation name is 'b6~1', location is LC4_C15, type is buried.
-- synthesized logic cell
_LC4_C15 = LCELL( a6);
-- Node name is 'b6'
-- Equation name is 'b6', type is output
b6 = !_LC4_C15;
-- Node name is 'b7~1'
-- Equation name is 'b7~1', location is LC2_B3, type is buried.
-- synthesized logic cell
_LC2_B3 = LCELL( a7);
-- Node name is 'b7'
-- Equation name is 'b7', type is output
b7 = _LC2_B3;
Project Information e:\mydds\verilog\tte.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 21,734K
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