Project Information            e:\esd-5_sample\dds-128-modu\verilog\mytest.rpt

MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 04/08/2007 16:34:36

Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input Output Bidir  Memory  Memory  			 LCs
POF       Device          Pins  Pins   Pins   Bits % Utilized  LCs  % Utilized

mytest    EPF10K10LC84-3   16     19     0    3840      62 %    244      42 %

User Pins:                 16     19     0  



Project Information            e:\esd-5_sample\dds-128-modu\verilog\mytest.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

mytest@19                         clk
mytest@67                         col0
mytest@66                         col1
mytest@65                         col2
mytest@64                         col3
mytest@69                         da_cs
mytest@58                         da_out0
mytest@54                         da_out1
mytest@53                         da_out2
mytest@52                         da_out3
mytest@51                         da_out4
mytest@50                         da_out5
mytest@49                         da_out6
mytest@48                         da_out7
mytest@70                         da0832wr
mytest@2                          DC
mytest@17                         int0
mytest@16                         Key0
mytest@11                         Key1
mytest@10                         Key2
mytest@9                          Key3
mytest@73                         Mdata0
mytest@78                         Mdata1
mytest@79                         Mdata2
mytest@80                         Mdata3
mytest@81                         Mdata4
mytest@83                         Mdata5
mytest@3                          Mdata6
mytest@5                          Mdata7
mytest@84                         Mh
mytest@7                          PCS
mytest@62                         row0
mytest@61                         row1
mytest@60                         row2
mytest@59                         row3


Project Information            e:\esd-5_sample\dds-128-modu\verilog\mytest.rpt

** EMBEDDED ARRAYS **


|phaserom1:20|lpm_rom:lpm_rom_component|altrom:srom|content: MEMORY (
               width        =    8;
               depth        =  256;
               segmentsize  =  256;
               mode         = MEM_READONLY#MEM_INITIALIZED;
               file         = "G:/RESEARCH/Tjx-EXPERIMENT/ESD-5_Sample/DDS-128-modu/verilog/pr.mif";
         )
         OF SEGMENTS (
               |phaserom1:20|lpm_rom:lpm_rom_component|altrom:srom|segment0_7,
               |phaserom1:20|lpm_rom:lpm_rom_component|altrom:srom|segment0_6,
               |phaserom1:20|lpm_rom:lpm_rom_component|altrom:srom|segment0_5,
               |phaserom1:20|lpm_rom:lpm_rom_component|altrom:srom|segment0_4,
               |phaserom1:20|lpm_rom:lpm_rom_component|altrom:srom|segment0_3,
               |phaserom1:20|lpm_rom:lpm_rom_component|altrom:srom|segment0_2,
               |phaserom1:20|lpm_rom:lpm_rom_component|altrom:srom|segment0_1,
               |phaserom1:20|lpm_rom:lpm_rom_component|altrom:srom|segment0_0		/* This segment is removed by logic synthesis */
);



|phaserom2:69|lpm_rom:lpm_rom_component|altrom:srom|content: MEMORY (
               width        =    8;
               depth        =  256;
               segmentsize  =  256;
               mode         = MEM_READONLY#MEM_INITIALIZED;
               file         = "G:/RESEARCH/Tjx-EXPERIMENT/ESD-5_Sample/DDS-128-modu/verilog/pr0.mif";
         )
         OF SEGMENTS (
               |phaserom2:69|lpm_rom:lpm_rom_component|altrom:srom|segment0_7,
               |phaserom2:69|lpm_rom:lpm_rom_component|altrom:srom|segment0_6,
               |phaserom2:69|lpm_rom:lpm_rom_component|altrom:srom|segment0_5,
               |phaserom2:69|lpm_rom:lpm_rom_component|altrom:srom|segment0_4,
               |phaserom2:69|lpm_rom:lpm_rom_component|altrom:srom|segment0_3,
               |phaserom2:69|lpm_rom:lpm_rom_component|altrom:srom|segment0_2,
               |phaserom2:69|lpm_rom:lpm_rom_component|altrom:srom|segment0_1,
               |phaserom2:69|lpm_rom:lpm_rom_component|altrom:srom|segment0_0
);




Project Information            e:\esd-5_sample\dds-128-modu\verilog\mytest.rpt

** FILE HIERARCHY **



|kbscan:81|
|kbscan:81|lpm_add_sub:44|
|kbscan:81|lpm_add_sub:44|addcore:adder|
|kbscan:81|lpm_add_sub:44|altshift:result_ext_latency_ffs|
|kbscan:81|lpm_add_sub:44|altshift:carry_ext_latency_ffs|
|kbscan:81|lpm_add_sub:44|altshift:oflow_ext_latency_ffs|
|phaserom1:20|
|phaserom1:20|lpm_rom:lpm_rom_component|
|phaserom1:20|lpm_rom:lpm_rom_component|altrom:srom|
|phaserom2:69|
|phaserom2:69|lpm_rom:lpm_rom_component|
|phaserom2:69|lpm_rom:lpm_rom_component|altrom:srom|
|cmdctrl:44|
|mainctrl:45|
|mainctrl:45|lpm_add_sub:117|
|mainctrl:45|lpm_add_sub:117|addcore:adder|
|mainctrl:45|lpm_add_sub:117|altshift:result_ext_latency_ffs|
|mainctrl:45|lpm_add_sub:117|altshift:carry_ext_latency_ffs|
|mainctrl:45|lpm_add_sub:117|altshift:oflow_ext_latency_ffs|
|mainctrl:45|lpm_add_sub:118|
|mainctrl:45|lpm_add_sub:118|addcore:adder|
|mainctrl:45|lpm_add_sub:118|altshift:result_ext_latency_ffs|
|mainctrl:45|lpm_add_sub:118|altshift:carry_ext_latency_ffs|
|mainctrl:45|lpm_add_sub:118|altshift:oflow_ext_latency_ffs|
|mainctrl:45|lpm_add_sub:119|
|mainctrl:45|lpm_add_sub:119|addcore:adder|
|mainctrl:45|lpm_add_sub:119|altshift:result_ext_latency_ffs|
|mainctrl:45|lpm_add_sub:119|altshift:carry_ext_latency_ffs|
|mainctrl:45|lpm_add_sub:119|altshift:oflow_ext_latency_ffs|
|tiao:47|
|tiao:47|lpm_add_sub:88|
|tiao:47|lpm_add_sub:88|addcore:adder|
|tiao:47|lpm_add_sub:88|altshift:result_ext_latency_ffs|
|tiao:47|lpm_add_sub:88|altshift:carry_ext_latency_ffs|
|tiao:47|lpm_add_sub:88|altshift:oflow_ext_latency_ffs|
|tiao:47|lpm_add_sub:89|
|tiao:47|lpm_add_sub:89|addcore:adder|
|tiao:47|lpm_add_sub:89|altshift:result_ext_latency_ffs|
|tiao:47|lpm_add_sub:89|altshift:carry_ext_latency_ffs|
|tiao:47|lpm_add_sub:89|altshift:oflow_ext_latency_ffs|
|huan3:71|
|chengfa2:72|
|chengfa2:72|one_bit_adder:U_0_0|
|chengfa2:72|one_bit_adder:U_0_1|
|chengfa2:72|one_bit_adder:U_0_2|
|chengfa2:72|one_bit_adder:U_0_3|
|chengfa2:72|one_bit_adder:U_0_4|
|chengfa2:72|one_bit_adder:U_0_5|
|chengfa2:72|one_bit_adder:U_0_6|
|chengfa2:72|one_bit_adder:U_0_7|
|chengfa2:72|one_bit_adder:U_1_0|
|chengfa2:72|one_bit_adder:U_1_1|
|chengfa2:72|one_bit_adder:U_1_2|
|chengfa2:72|one_bit_adder:U_1_3|
|chengfa2:72|one_bit_adder:U_1_4|
|chengfa2:72|one_bit_adder:U_1_5|
|chengfa2:72|one_bit_adder:U_1_6|
|chengfa2:72|one_bit_adder:U_1_7|
|chengfa2:72|one_bit_adder:U_2_0|
|chengfa2:72|one_bit_adder:U_2_1|
|chengfa2:72|one_bit_adder:U_2_2|
|chengfa2:72|one_bit_adder:U_2_3|
|chengfa2:72|one_bit_adder:U_2_4|
|chengfa2:72|one_bit_adder:U_2_5|
|chengfa2:72|one_bit_adder:U_2_6|
|chengfa2:72|one_bit_adder:U_2_7|
|chengfa2:72|one_bit_adder:U_3_0|
|chengfa2:72|one_bit_adder:U_3_1|
|chengfa2:72|one_bit_adder:U_3_2|
|chengfa2:72|one_bit_adder:U_3_3|
|chengfa2:72|one_bit_adder:U_3_4|
|chengfa2:72|one_bit_adder:U_3_5|
|chengfa2:72|one_bit_adder:U_3_6|
|chengfa2:72|one_bit_adder:U_3_7|
|chengfa2:72|one_bit_adder:U_4_0|
|chengfa2:72|one_bit_adder:U_4_1|
|chengfa2:72|one_bit_adder:U_4_2|
|chengfa2:72|one_bit_adder:U_4_3|
|chengfa2:72|one_bit_adder:U_4_4|
|chengfa2:72|one_bit_adder:U_4_5|
|chengfa2:72|one_bit_adder:U_4_6|
|chengfa2:72|one_bit_adder:U_4_7|