?? chengfa2.vhd
字號:
--8位無符號的乘法器，但實際上做了7位乘法
library IEEE;
use IEEE.std_logic_1164.all;
entity one_bit_adder is
port (
A: in STD_LOGIC;
B: in STD_LOGIC;
C_in: in STD_LOGIC;
S: out STD_LOGIC;
C_out: out STD_LOGIC
);
end one_bit_adder;
architecture one_bit_adder of one_bit_adder is
begin
S <= A xor B xor C_in;
C_out <= (A and B) or (C_in and (A xor B));
end one_bit_adder;
library IEEE;
use IEEE.std_logic_1164.all;
entity chengfa2 is
port (
A: in STD_LOGIC_VECTOR (7 downto 0);
B: in STD_LOGIC_VECTOR (7 downto 0);
data_out: out STD_LOGIC_VECTOR (15 downto 0)
);
end chengfa2;
architecture multi_arch of chengfa2 is
signal A_MULT_B0: STD_LOGIC_VECTOR (7 downto 0);
signal A_MULT_B1: STD_LOGIC_VECTOR (7 downto 0);
signal A_MULT_B2: STD_LOGIC_VECTOR (7 downto 0);
signal A_MULT_B3: STD_LOGIC_VECTOR (7 downto 0);
signal A_MULT_B4: STD_LOGIC_VECTOR (7 downto 0);
signal A_MULT_B5: STD_LOGIC_VECTOR (7 downto 0);
signal A_MULT_B6: STD_LOGIC_VECTOR (7 downto 0);
signal A_MULT_B7: STD_LOGIC_VECTOR (7 downto 0);
signal S_TEMP1: STD_LOGIC_VECTOR (6 downto 0);
signal S_TEMP2: STD_LOGIC_VECTOR (6 downto 0);
signal S_TEMP3: STD_LOGIC_VECTOR (6 downto 0);
signal S_TEMP4: STD_LOGIC_VECTOR (6 downto 0);
signal S_TEMP5: STD_LOGIC_VECTOR (6 downto 0);
signal S_TEMP6: STD_LOGIC_VECTOR (6 downto 0);
signal C_out_B0: STD_LOGIC_VECTOR (7 downto 0);
signal C_out_B1: STD_LOGIC_VECTOR (7 downto 0);
signal C_out_B2: STD_LOGIC_VECTOR (7 downto 0);
signal C_out_B3: STD_LOGIC_VECTOR (7 downto 0);
signal C_out_B4: STD_LOGIC_VECTOR (7 downto 0);
signal C_out_B5: STD_LOGIC_VECTOR (7 downto 0);
signal C_out_B6: STD_LOGIC_VECTOR (7 downto 0);
signal C_TEMP : STD_LOGIC_VECTOR (15 downto 0);
signal ZERO: STD_LOGIC;
component one_bit_adder
port (
A: in STD_LOGIC;
B: in STD_LOGIC;
C_in: in STD_LOGIC;
S: out STD_LOGIC;
C_out: out STD_LOGIC
);
end component;
begin
U_0_0:one_bit_adder port map(
A=>A_MULT_B0(1),B=>A_MULT_B1(0),C_in=>ZERO,
S=>C_TEMP(1),C_out=>C_OUT_B0(0));
U_0_1:one_bit_adder port map(
A=>A_MULT_B0(2),B=>A_MULT_B1(1),C_in=>C_OUT_B0(0),
S=>S_TEMP1(0),C_out=>C_OUT_B0(1));
U_0_2:one_bit_adder port map(
A=>A_MULT_B0(3),B=>A_MULT_B1(2),C_in=>C_OUT_B0(1),
S=>S_TEMP1(1),C_out=>C_OUT_B0(2));
U_0_3:one_bit_adder port map(
A=>A_MULT_B0(4),B=>A_MULT_B1(3),C_in=>C_OUT_B0(2),
S=>S_TEMP1(2),C_out=>C_OUT_B0(3));
U_0_4:one_bit_adder port map(
A=>A_MULT_B0(5),B=>A_MULT_B1(4),C_in=>C_OUT_B0(3),
S=>S_TEMP1(3),C_out=>C_OUT_B0(4));
U_0_5:one_bit_adder port map(
A=>A_MULT_B0(6),B=>A_MULT_B1(5),C_in=>C_OUT_B0(4),
S=>S_TEMP1(4),C_out=>C_OUT_B0(5));
U_0_6:one_bit_adder port map(
A=>A_MULT_B0(7),B=>A_MULT_B1(6),C_in=>C_OUT_B0(5),
S=>S_TEMP1(5),C_out=>C_OUT_B0(6));
U_0_7:one_bit_adder port map(
A=>ZERO,B=>A_MULT_B1(7),C_in=>C_OUT_B0(6),
S=>S_TEMP1(6),C_out=>C_OUT_B0(7));
U_1_0:one_bit_adder port map(
A=>A_MULT_B2(0),B=>S_TEMP1(0),C_in=>ZERO,
S=>C_TEMP(2),C_out=>C_OUT_B1(0));
U_1_1:one_bit_adder port map(
A=>A_MULT_B2(1),B=>S_TEMP1(1),C_in=>C_OUT_B1(0),
S=>S_TEMP2(0),C_out=>C_OUT_B1(1));
U_1_2:one_bit_adder port map(
A=>A_MULT_B2(2),B=>S_TEMP1(2),C_in=>C_OUT_B1(1),
S=>S_TEMP2(1),C_out=>C_OUT_B1(2));
U_1_3:one_bit_adder port map(
A=>A_MULT_B2(3),B=>S_TEMP1(3),C_in=>C_OUT_B1(2),
S=>S_TEMP2(2),C_out=>C_OUT_B1(3));
U_1_4:one_bit_adder port map(
A=>A_MULT_B2(4),B=>S_TEMP1(4),C_in=>C_OUT_B1(3),
S=>S_TEMP2(3),C_out=>C_OUT_B1(4));
U_1_5:one_bit_adder port map(
A=>A_MULT_B2(5),B=>S_TEMP1(5),C_in=>C_OUT_B1(4),
S=>S_TEMP2(4),C_out=>C_OUT_B1(5));
U_1_6:one_bit_adder port map(
A=>A_MULT_B2(6),B=>S_TEMP1(6),C_in=>C_OUT_B1(5),
S=>S_TEMP2(5),C_out=>C_OUT_B1(6));
U_1_7:one_bit_adder port map(
A=>A_MULT_B2(7),B=>ZERO,C_in=>C_OUT_B1(6),
S=>S_TEMP2(6),C_out=>C_OUT_B1(7));
U_2_0:one_bit_adder port map(
A=>A_MULT_B3(0),B=>S_TEMP2(0),C_in=>ZERO,
S=>C_TEMP(3),C_out=>C_OUT_B2(0));
U_2_1:one_bit_adder port map(
A=>A_MULT_B3(1),B=>S_TEMP2(1),C_in=>C_OUT_B2(0),
S=>S_TEMP3(0),C_out=>C_OUT_B2(1));
U_2_2:one_bit_adder port map(
A=>A_MULT_B3(2),B=>S_TEMP2(2),C_in=>C_OUT_B2(1),
S=>S_TEMP3(1),C_out=>C_OUT_B2(2));
U_2_3:one_bit_adder port map(
A=>A_MULT_B3(3),B=>S_TEMP2(3),C_in=>C_OUT_B2(2),
S=>S_TEMP3(2),C_out=>C_OUT_B2(3));
U_2_4:one_bit_adder port map(
A=>A_MULT_B3(4),B=>S_TEMP2(4),C_in=>C_OUT_B2(3),
S=>S_TEMP3(3),C_out=>C_OUT_B2(4));
U_2_5:one_bit_adder port map(
A=>A_MULT_B3(5),B=>S_TEMP2(5),C_in=>C_OUT_B2(4),
S=>S_TEMP3(4),C_out=>C_OUT_B2(5));
U_2_6:one_bit_adder port map(
A=>A_MULT_B3(6),B=>S_TEMP2(6),C_in=>C_OUT_B2(5),
S=>S_TEMP3(5),C_out=>C_OUT_B2(6));
U_2_7:one_bit_adder port map(
A=>A_MULT_B3(7),B=>ZERO,C_in=>C_OUT_B2(6),
S=>S_TEMP3(6),C_out=>C_OUT_B2(7));
U_3_0:one_bit_adder port map(
A=>A_MULT_B4(0),B=>S_TEMP3(0),C_in=>ZERO,
S=>C_TEMP(4),C_out=>C_OUT_B3(0));
U_3_1:one_bit_adder port map(
A=>A_MULT_B4(1),B=>S_TEMP3(1),C_in=>C_OUT_B3(0),
S=>S_TEMP4(0),C_out=>C_OUT_B3(1));
U_3_2:one_bit_adder port map(
A=>A_MULT_B4(2),B=>S_TEMP3(2),C_in=>C_OUT_B3(1),
S=>S_TEMP4(1),C_out=>C_OUT_B3(2));
U_3_3:one_bit_adder port map(
A=>A_MULT_B4(3),B=>S_TEMP3(3),C_in=>C_OUT_B3(2),
S=>S_TEMP4(2),C_out=>C_OUT_B3(3));
U_3_4:one_bit_adder port map(
A=>A_MULT_B4(4),B=>S_TEMP3(4),C_in=>C_OUT_B3(3),
S=>S_TEMP4(3),C_out=>C_OUT_B3(4));
U_3_5:one_bit_adder port map(
A=>A_MULT_B4(5),B=>S_TEMP3(5),C_in=>C_OUT_B3(4),
S=>S_TEMP4(4),C_out=>C_OUT_B3(5));
U_3_6:one_bit_adder port map(
A=>A_MULT_B4(6),B=>S_TEMP3(6),C_in=>C_OUT_B3(5),
S=>S_TEMP4(5),C_out=>C_OUT_B3(6));
U_3_7:one_bit_adder port map(
A=>A_MULT_B4(7),B=>ZERO,C_in=>C_OUT_B3(6),
S=>S_TEMP4(6),C_out=>C_OUT_B3(7));
U_4_0:one_bit_adder port map(
A=>A_MULT_B5(0),B=>S_TEMP4(0),C_in=>ZERO,
S=>C_TEMP(5),C_out=>C_OUT_B4(0));
U_4_1:one_bit_adder port map(
A=>A_MULT_B5(1),B=>S_TEMP4(1),C_in=>C_OUT_B4(0),
S=>S_TEMP5(0),C_out=>C_OUT_B4(1));
U_4_2:one_bit_adder port map(
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