library IEEE;
            use IEEE.std_logic_1164.all;

            entity oba is
            port (
            A: in STD_LOGIC;
            B: in STD_LOGIC;
            C_in: in STD_LOGIC;
            S: out STD_LOGIC;
            C_out: out STD_LOGIC
            );
            end oba;

            architecture mi of oba is
            begin

            S <= A xor B xor C_in;
            C_out <= (A and B) or (C_in and (A xor B));

            end mi;