?? huan.rpt
字號:
- 5 - B 02 DFFE + 3 1 1 0 :24
- 7 - B 02 DFFE + 2 1 1 0 :26
- 8 - B 02 DFFE + 4 0 1 0 :28
- 5 - A 14 DFFE + 3 0 1 0 :30
- 2 - A 14 DFFE + 2 0 1 0 :32
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\mydds\verilog\huan.rpt
huan
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 2/ 48( 4%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
B: 5/ 96( 5%) 4/ 48( 8%) 0/ 48( 0%) 3/16( 18%) 6/16( 37%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\mydds\verilog\huan.rpt
huan
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 clk
Device-Specific Information: e:\mydds\verilog\huan.rpt
huan
** EQUATIONS **
A7 : INPUT;
A8 : INPUT;
A9 : INPUT;
A10 : INPUT;
A11 : INPUT;
A12 : INPUT;
A13 : INPUT;
A15 : INPUT;
clk : INPUT;
-- Node name is 'aout0'
-- Equation name is 'aout0', type is output
aout0 = _LC2_A14;
-- Node name is 'aout1'
-- Equation name is 'aout1', type is output
aout1 = _LC5_A14;
-- Node name is 'aout2'
-- Equation name is 'aout2', type is output
aout2 = _LC8_B2;
-- Node name is 'aout3'
-- Equation name is 'aout3', type is output
aout3 = _LC7_B2;
-- Node name is 'aout4'
-- Equation name is 'aout4', type is output
aout4 = _LC5_B2;
-- Node name is 'aout5'
-- Equation name is 'aout5', type is output
aout5 = _LC1_B2;
-- Node name is 'aout6'
-- Equation name is 'aout6', type is output
aout6 = _LC3_B2;
-- Node name is 'aout7'
-- Equation name is 'aout7', type is output
aout7 = _LC4_B2;
-- Node name is '|LPM_ADD_SUB:139|addcore:adder|:125' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_B2', type is buried
_LC2_B2 = LCELL( _EQ001);
_EQ001 = !A7 & !A8 & !A9;
-- Node name is '|LPM_ADD_SUB:139|addcore:adder|:133' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B2', type is buried
_LC6_B2 = LCELL( _EQ002);
_EQ002 = !A10 & !A11 & _LC2_B2;
-- Node name is ':18'
-- Equation name is '_LC4_B2', type is buried
_LC4_B2 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !A12 & !A13 & A15 & _LC6_B2
# !A15 & !_LC6_B2
# A12 & !A15
# A13 & !A15;
-- Node name is ':20'
-- Equation name is '_LC3_B2', type is buried
_LC3_B2 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !A12 & !A13 & !A15 & _LC6_B2
# !A12 & A13 & A15 & _LC6_B2
# !A13 & A15 & !_LC6_B2
# A12 & !A13 & A15
# A13 & !A15 & !_LC6_B2
# A12 & A13 & !A15;
-- Node name is ':22'
-- Equation name is '_LC1_B2', type is buried
_LC1_B2 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = A12 & A15 & _LC6_B2
# !A12 & A15 & !_LC6_B2
# !A12 & !A15 & _LC6_B2
# A12 & !A15 & !_LC6_B2;
-- Node name is ':24'
-- Equation name is '_LC5_B2', type is buried
_LC5_B2 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = !A10 & !A11 & !A15 & _LC2_B2
# !A10 & A11 & A15 & _LC2_B2
# !A11 & A15 & !_LC2_B2
# A10 & !A11 & A15
# A11 & !A15 & !_LC2_B2
# A10 & A11 & !A15;
-- Node name is ':26'
-- Equation name is '_LC7_B2', type is buried
_LC7_B2 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = !A10 & !A15 & _LC2_B2
# A10 & A15 & _LC2_B2
# !A10 & A15 & !_LC2_B2
# A10 & !A15 & !_LC2_B2;
-- Node name is ':28'
-- Equation name is '_LC8_B2', type is buried
_LC8_B2 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = A8 & !A9 & A15
# A7 & !A9 & A15
# !A7 & !A8 & A9 & A15
# !A7 & !A8 & !A9 & !A15
# A8 & A9 & !A15
# A7 & A9 & !A15;
-- Node name is ':30'
-- Equation name is '_LC5_A14', type is buried
_LC5_A14 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = A7 & !A8 & A15
# !A7 & A8 & A15
# !A7 & !A8 & !A15
# A7 & A8 & !A15;
-- Node name is ':32'
-- Equation name is '_LC2_A14', type is buried
_LC2_A14 = DFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = A7 & A15
# !A7 & !A15;
Project Information e:\mydds\verilog\huan.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 27,580K
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