library IEEE;
            use IEEE.std_logic_1164.all;
            use ieee.std_logic_unsigned.all;

            entity huan2 is
            port (
            A: in STD_LOGIC_vector(15 downto 0);
            aout: out STD_LOGIC_vector(7 downto 0)
            );
            end huan2;

            architecture mmm of huan2 is
            begin

            aout<=A(15 downto 8);
            end mmm;