07:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
08:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
14:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
15:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
16:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
17:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
18:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
19:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
20:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
21:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
22:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
23:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
24:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:                      d:\newvhd\mytest\cmdctrl.rpt
cmdctrl

** CLOCK SIGNALS **

Type     Fan-out       Name
INPUT       18         PCS


Device-Specific Information:                      d:\newvhd\mytest\cmdctrl.rpt
cmdctrl

** EQUATIONS **

DC       : INPUT;
Mdata0   : INPUT;
Mdata1   : INPUT;
Mdata2   : INPUT;
Mdata3   : INPUT;
Mdata4   : INPUT;
Mdata5   : INPUT;
Mdata6   : INPUT;
Mdata7   : INPUT;
Mh       : INPUT;
PCS      : INPUT;

-- Node name is 'Cmdout0' 
-- Equation name is 'Cmdout0', type is output 
Cmdout0  =  _LC2_B3;

-- Node name is 'Cmdout1' 
-- Equation name is 'Cmdout1', type is output 
Cmdout1  =  _LC4_B3;

-- Node name is 'Div0' 
-- Equation name is 'Div0', type is output 
Div0     =  _LC1_A24;

-- Node name is 'Div1' 
-- Equation name is 'Div1', type is output 
Div1     =  _LC8_A24;

-- Node name is 'Div2' 
-- Equation name is 'Div2', type is output 
Div2     =  _LC5_A24;

-- Node name is 'Div3' 
-- Equation name is 'Div3', type is output 
Div3     =  _LC7_A24;

-- Node name is 'Div4' 
-- Equation name is 'Div4', type is output 
Div4     =  _LC6_B3;

-- Node name is 'Mout0' 
-- Equation name is 'Mout0', type is output 
Mout0    =  M0;

-- Node name is 'Mout1' 
-- Equation name is 'Mout1', type is output 
Mout1    =  M1;

-- Node name is 'Mout2' 
-- Equation name is 'Mout2', type is output 
Mout2    =  M2;

-- Node name is 'Mout3' 
-- Equation name is 'Mout3', type is output 
Mout3    =  M3;

-- Node name is 'Mout4' 
-- Equation name is 'Mout4', type is output 
Mout4    =  M4;

-- Node name is 'Mout5' 
-- Equation name is 'Mout5', type is output 
Mout5    =  M5;

-- Node name is 'Mout6' 
-- Equation name is 'Mout6', type is output 
Mout6    =  M6;

-- Node name is 'Mout7' 
-- Equation name is 'Mout7', type is output 
Mout7    =  M7;

-- Node name is 'Mout8' 
-- Equation name is 'Mout8', type is output 
Mout8    =  M8;

-- Node name is 'Mout9' 
-- Equation name is 'Mout9', type is output 
Mout9    =  M9;

-- Node name is 'Mout10' 
-- Equation name is 'Mout10', type is output 
Mout10   =  M10;

-- Node name is ':82' = 'M0' 
-- Equation name is 'M0', location is LC1_B3, type is buried.
M0       = DFFE( _EQ001, GLOBAL(!PCS),  VCC,  VCC,  DC);
  _EQ001 =  Mh &  M0
         #  Mdata0 & !Mh;

-- Node name is ':81' = 'M1' 
-- Equation name is 'M1', location is LC3_B3, type is buried.
M1       = DFFE( _EQ002, GLOBAL(!PCS),  VCC,  VCC,  DC);
  _EQ002 =  Mh &  M1
         #  Mdata1 & !Mh;

-- Node name is ':80' = 'M2' 
-- Equation name is 'M2', location is LC5_C15, type is buried.
M2       = DFFE( _EQ003, GLOBAL(!PCS),  VCC,  VCC,  DC);
  _EQ003 =  Mh &  M2
         #  Mdata2 & !Mh;

-- Node name is ':79' = 'M3' 
-- Equation name is 'M3', location is LC2_A24, type is buried.
M3       = DFFE( _EQ004, GLOBAL(!PCS),  VCC,  VCC,  DC);
  _EQ004 =  Mh &  M3
         #  Mdata3 & !Mh;

-- Node name is ':78' = 'M4' 
-- Equation name is 'M4', location is LC4_A24, type is buried.
M4       = DFFE( _EQ005, GLOBAL(!PCS),  VCC,  VCC,  DC);
  _EQ005 =  Mh &  M4
         #  Mdata4 & !Mh;

-- Node name is ':77' = 'M5' 
-- Equation name is 'M5', location is LC3_A24, type is buried.
M5       = DFFE( _EQ006, GLOBAL(!PCS),  VCC,  VCC,  DC);
  _EQ006 =  Mh &  M5
         #  Mdata5 & !Mh;

-- Node name is ':76' = 'M6' 
-- Equation name is 'M6', location is LC6_A24, type is buried.
M6       = DFFE( _EQ007, GLOBAL(!PCS),  VCC,  VCC,  DC);
  _EQ007 =  Mh &  M6
         #  Mdata6 & !Mh;

-- Node name is ':75' = 'M7' 
-- Equation name is 'M7', location is LC5_B3, type is buried.
M7       = DFFE( _EQ008, GLOBAL(!PCS),  VCC,  VCC,  DC);
  _EQ008 =  Mh &  M7
         #  Mdata7 & !Mh;

-- Node name is ':74' = 'M8' 
-- Equation name is 'M8', location is LC7_B3, type is buried.
M8       = DFFE( _EQ009, GLOBAL(!PCS),  VCC,  VCC,  DC);
  _EQ009 = !Mh &  M8
         #  Mdata0 &  Mh;

-- Node name is ':73' = 'M9' 
-- Equation name is 'M9', location is LC8_B3, type is buried.
M9       = DFFE( _EQ010, GLOBAL(!PCS),  VCC,  VCC,  DC);
  _EQ010 = !Mh &  M9
         #  Mdata1 &  Mh;

-- Node name is ':72' = 'M10' 
-- Equation name is 'M10', location is LC3_C15, type is buried.
M10      = DFFE( _EQ011, GLOBAL(!PCS),  VCC,  VCC,  DC);
  _EQ011 = !Mh &  M10
         #  Mdata2 &  Mh;

-- Node name is ':113' 
-- Equation name is '_LC4_B3', type is buried 
_LC4_B3  = DFFE( _EQ012, GLOBAL(!PCS),  VCC,  VCC,  VCC);
  _EQ012 =  DC &  _LC4_B3
         # !DC &  Mdata1;

-- Node name is ':114' 
-- Equation name is '_LC2_B3', type is buried 
_LC2_B3  = DFFE( _EQ013, GLOBAL(!PCS),  VCC,  VCC,  VCC);
  _EQ013 =  DC &  _LC2_B3
         # !DC &  Mdata0;

-- Node name is ':132' 
-- Equation name is '_LC6_B3', type is buried 
_LC6_B3  = DFFE( _EQ014, GLOBAL(!PCS),  VCC,  VCC,  DC);
  _EQ014 =  _LC6_B3 & !Mh
         #  Mdata7 &  Mh;

-- Node name is ':133' 
-- Equation name is '_LC7_A24', type is buried 
_LC7_A24 = DFFE( _EQ015, GLOBAL(!PCS),  VCC,  VCC,  DC);
  _EQ015 =  _LC7_A24 & !Mh
         #  Mdata6 &  Mh;

-- Node name is ':134' 
-- Equation name is '_LC5_A24', type is buried 
_LC5_A24 = DFFE( _EQ016, GLOBAL(!PCS),  VCC,  VCC,  DC);
  _EQ016 =  _LC5_A24 & !Mh
         #  Mdata5 &  Mh;

-- Node name is ':135' 
-- Equation name is '_LC8_A24', type is buried 
_LC8_A24 = DFFE( _EQ017, GLOBAL(!PCS),  VCC,  VCC,  DC);
  _EQ017 =  _LC8_A24 & !Mh
         #  Mdata4 &  Mh;

-- Node name is ':136' 
-- Equation name is '_LC1_A24', type is buried 
_LC1_A24 = DFFE( _EQ018, GLOBAL(!PCS),  VCC,  VCC,  DC);
  _EQ018 =  _LC1_A24 & !Mh
         #  Mdata3 &  Mh;



Project Information                               d:\newvhd\mytest\cmdctrl.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 25,413K