--FPGA控制7279的程序

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_ARITH.all;
use IEEE.std_logic_UNSIGNED.all;

entity hd7279 is
	port (
		--以下是引腳信號
	
		CLK       :IN      STD_LOGIC;  --系統(tǒng)時鐘
		RST_N     :IN      STD_LOGIC;  --系統(tǒng)復(fù)位
	--	CLK_S     :IN      STD_LOGIC;  --7279時序的狀態(tài)機(jī)時鐘,周期為20us
		--外部控制接口與本模塊之間的信號
		--WR_N      :IN      STD_LOGIC;  --外部寫信號
		--RD_N      :IN      STD_LOGIC;  --外部讀信號
		--KEY_EN    :OUT     STD_LOGIC;  --存在有效鍵值, 高電平為存在有效鍵值, 外部接口讀走數(shù)據(jù)后變低
		--ADDR  	  :IN      STD_LOGIC_VECTOR(2 downto 0);  --地址信號
		D_BUS1,D_BUS2,D_BUS3 	  :IN      STD_LOGIC_VECTOR(6 downto 0);  --指令,數(shù)據(jù)輸入及鍵盤值輸出
		--與7279之間的信號
		--KEY7279   :IN      STD_LOGIC;  --7279的鍵盤信號，有鍵按下時為低電平，平時為高電平
			key7279: in STD_LOGIC; 
		abc : in STD_LOGIC_VECTOR(2 downto 0);
		D_BUS4 	  :IN      STD_LOGIC_VECTOR(6 downto 0);
			CLK7279,clk2   :OUT     STD_LOGIC;  --7279的時鐘信號
		CS7279    :OUT     STD_LOGIC;  --7279的片選信號
	
		DAT7279   :INOUT   STD_LOGIC; --7279數(shù)據(jù)信號
		channel: out STD_LOGIC_VECTOR(2 downto 0)
		--OUT7279   :OUT     STD_LOGIC_VECTOR(7 downto 0)   --7279鍵盤鍵值輸出信號,測試時用
		);
end hd7279;

ARCHITECTURE behav OF hd7279 IS
CONSTANT NDC_7279	: std_logic_vector (7 downto 0) := x"90";  --下載數(shù)據(jù)不譯碼,
CONSTANT RDKY_7279	: std_logic_vector (7 downto 0) := x"15";  --讀鍵盤數(shù)據(jù)指令 
   TYPE STATE_TYPE is (IDLE, START, START_DELAY, SHIFT_CMD_LOW, 
					SHIFT_CMD_HIGH,	NEXT_DELAY,  SHIFT_DATA_LOW, SHIFT_DATA_HIGH, 
					SHIFT_KEY_LOW, SHIFT_KEY_HIGH, SHIFT_KEY_HIGH1, FINISH );
signal state : STATE_TYPE;
SIGNAL data_tmp     : STD_LOGIC_VECTOR (7 downto 0); --進(jìn)入START狀態(tài)后,操作數(shù)據(jù)緩存
signal count: integer; 
SIGNAL seg_cnt		: INTEGER RANGE 0 to 7;			 --數(shù)碼管計數(shù)器,從右到左一共8個數(shù)碼管
SIGNAL cmd_tmp      : STD_LOGIC_VECTOR (7 downto 0); --保存操作命令到移位緩存
SIGNAL delay_cnt	: INTEGER RANGE 0 to 3;
SIGNAL scmd_cnt     : INTEGER RANGE 0 to 7;    
signal cp2:std_logic;
signal t:std_logic;
SIGNAL sdata_cnt    : INTEGER RANGE 0 to 7;
signal dp,dp1		: std_logic; 
signal key_7279_tmp: STD_LOGIC_VECTOR (7 downto 0);
signal key_7279: STD_LOGIC_VECTOR (7 downto 0);
signal chann: STD_LOGIC_VECTOR(2 downto 0);
begin
	dp<='0';dp1<='1';
p1: process(clk)                    ----分頻
begin
if (clk'event and clk='1') then
if (count =200) then
count<= 0;
t <= not t;
else
count<= count + 1;
end if;
end if;
cp2<=t;clk2<=cp2;
end process p1;

p2:process(cp2)
begin
  if(RST_N='0')  then
     state <= IDLE;
		
		CS7279 <= '1';
		CLK7279 <= '0';
		DAT7279 <= 'Z';
		state <= IDLE;

	elsif (cp2'event and cp2='1') then
	  	
		case state is
			when IDLE =>
			   if (KEY7279 = '0') then
					cmd_tmp <= RDKY_7279;--為了測試讀鍵盤操作
					DAT7279 <= 'Z';
					 	
					
					state <= START; 
			  else
				  if (seg_cnt = 3) then
						seg_cnt <= 0;
				  else
						seg_cnt <= seg_cnt + 1;						
				  end if;
					cmd_tmp <= NDC_7279(7 downto 3) & CONV_STD_LOGIC_VECTOR(seg_cnt,3);
					if(seg_cnt=0) then
					data_tmp <= dp&D_bus1;
					end if;
					if(seg_cnt=1) then
					data_tmp<=dp&D_BUS2;
					end if;
					if(seg_cnt=2) then
					data_tmp<=dp1&D_BUS3;
					end if;
					if(seg_cnt=3) then
					data_tmp<=dp&D_BUS4;
					end if;
					state <= START; 
				end if;				
			when START =>
				delay_cnt <= 3;
				CS7279 <= '0';			--7279片選置低,開始4次延時,即80us
				CLK7279 <= '0';			--設(shè)置時鐘為低
				state <= START_DELAY;
			
			--開始發(fā)送命令字-------------------------------------------------
			when START_DELAY =>
				if (delay_cnt > 1) then
					delay_cnt <= delay_cnt - 1;
				else
					scmd_cnt <= 7;		--80us延時結(jié)束,開始送命令字
					state <= SHIFT_CMD_LOW;
				end if;
			when SHIFT_CMD_LOW =>		--1位數(shù)據(jù)送到數(shù)據(jù)線上
				DAT7279 <= cmd_tmp(scmd_cnt);	--用命令字的二級緩存做
				CLK7279 <= '1';			--時鐘信號由低變高
				state <= SHIFT_CMD_HIGH;
			when SHIFT_CMD_HIGH =>
				CLK7279 <= '0';		--一外時鐘后,時鐘信號由高變低
				if (scmd_cnt > 0) then
					scmd_cnt <= scmd_cnt - 1;
					state <= SHIFT_CMD_LOW;					
				--當(dāng)為雙字節(jié)操作時,交替間斷的延時
				else
					state <= NEXT_DELAY;
					delay_cnt <= 3;
				end if;
			
			--開始發(fā)送8位數(shù)據(jù)------------------------------------------------
			when NEXT_DELAY =>
				if (delay_cnt >1) then
					delay_cnt <= delay_cnt - 1;	--進(jìn)行讀取按鍵
				
				elsif (cmd_tmp = RDKY_7279) then	--當(dāng)為鍵盤接收指令時
					sdata_cnt <= 7;
					state <= SHIFT_KEY_LOW;			--進(jìn)行讀取按鍵
				else
					sdata_cnt <= 7;
					state <= SHIFT_DATA_LOW;		--80us延時結(jié)束,進(jìn)入數(shù)據(jù)傳輸
				end if;
			when SHIFT_DATA_LOW =>					--1位數(shù)據(jù)送到數(shù)據(jù)線上
				DAT7279 <= data_tmp(sdata_cnt);
				CLK7279 <= '1';						--時鐘信號由低變高
				state <= SHIFT_DATA_HIGH;
			when SHIFT_DATA_HIGH =>
				CLK7279 <= '0';						--時鐘信號由高變低
				if (sdata_cnt > 0) then					
					sdata_cnt <= sdata_cnt - 1;
					state <= SHIFT_DATA_LOW;
				else
					state <= FINISH;
				end if;
			--讀取按鍵值-----------------------------------------------------
			when SHIFT_KEY_LOW =>
				CLK7279 <= '1';						--時鐘信號由低變高,DAT7279變?yōu)檩斎霠顟B(tài)
				DAT7279 <= 'Z';
				state <= SHIFT_KEY_HIGH;
			when SHIFT_KEY_HIGH =>					--保證一個時鐘周期的建立時間
				--key_7279(sdata_cnt) <= DAT7279;
				key_7279_tmp(sdata_cnt) <= DAT7279;
				state <= SHIFT_KEY_HIGH1;
			when SHIFT_KEY_HIGH1 =>
				CLK7279 <= '0';						--低電平后為一個時鐘周期的保持時間
				if (sdata_cnt > 0) then					
					sdata_cnt <= sdata_cnt - 1;
					state <= SHIFT_KEY_LOW;
				else
					if (KEY7279 = '0') then			--當(dāng)讀取完后,KEY7279仍為0才能確定讀取的為有效值
						key_7279 <= key_7279_tmp;
					end if;
					state <= FINISH;
				end if;
			--結(jié)束操作-------------------------------------------------------
			when FINISH =>
				CS7279 <= '1';		--7279片選置高,結(jié)束操作
				state <= IDLE;				
			when others =>
				NULL;
				
		end case;
	end if;
	
	
end process p2;
--chann<=key_7279 (2 downto 0);
channel<=key_7279(2 downto 0); 
end;