///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor             : Xilinx
// \   \   \/    Version            : $Name: mig_v1_7 $
//  \   \        Application        : MIG
//  /   /        Filename           : mem_interface_top_cmp_rd_data_0.v
// /___/   /\    Date Last Modified : $Date: 2007/02/15 12:06:15 $
// \   \  /  \   Date Created       : Mon May 2 2005
//  \___\/\___\
//
// Device      : Virtex-4
// Design Name : DDR SDRAM
// Description: Contains the comaprison logic for the read data and generation
//              of an error flag.
///////////////////////////////////////////////////////////////////////////////

`timescale 1ns / 1ps
`include "../rtl/mem_interface_top_parameters_0.v"

module mem_interface_top_cmp_rd_data_0
  (
   input                        CLK,
   input                        RESET,
   input                        READ_DATA_VALID,
   input [(`data_width*2)-1:0]  APP_COMPARE_DATA,
   input [(`data_width*2)-1:0]  READ_DATA_FIFO_OUT,

   output reg                   ERROR
   );


   reg                       valid;
   reg [(`data_width/8)-1:0] byte_err_rising;
   reg [(`data_width/8)-1:0] byte_err_falling;
   reg                       valid_1;
   reg [(`data_width*2)-1:0] read_data_r;
   reg [(`data_width*2)-1:0] read_data_r2;
   reg [(`data_width*2)-1:0] write_data_r2;
   reg                       falling_error;
   reg                       rising_error;
   reg                       rst_r;
   wire [(`data_width/8)-1:0] byte_err_rising_w;
   wire [(`data_width/8)-1:0] byte_err_falling_w;
   wire [`data_width-1:0]     data_pattern_falling;
   wire [`data_width-1:0]     data_pattern_rising;
   wire [`data_width-1:0]     data_falling;
   wire [`data_width-1:0]     data_rising;
   wire                       byte_err_rising_a;
   wire                       byte_err_falling_a;


   assign data_falling         = read_data_r2[`data_width-1:0];
   assign data_rising          = read_data_r2[(`data_width*2)-1:`data_width];

   assign data_pattern_falling = write_data_r2[`data_width-1:0];
   assign data_pattern_rising  = write_data_r2[(`data_width*2)-1:`data_width];

   
  assign byte_err_falling_w[0] = ((valid_1  == 1'b1) &&
                 (data_falling[7:0] != data_pattern_falling[7:0]))? 1'b1:1'b0;



  assign byte_err_falling_w[1] = ((valid_1  == 1'b1) &&
                 (data_falling[15:8] != data_pattern_falling[15:8]))? 1'b1:1'b0;



  assign byte_err_falling_w[2] = ((valid_1  == 1'b1) &&
                 (data_falling[23:16] != data_pattern_falling[23:16]))? 1'b1:1'b0;



  assign byte_err_falling_w[3] = ((valid_1  == 1'b1) &&
                 (data_falling[31:24] != data_pattern_falling[31:24]))? 1'b1:1'b0;



  assign byte_err_falling_w[4] = ((valid_1  == 1'b1) &&
                 (data_falling[39:32] != data_pattern_falling[39:32]))? 1'b1:1'b0;



  assign byte_err_falling_w[5] = ((valid_1  == 1'b1) &&
                 (data_falling[47:40] != data_pattern_falling[47:40]))? 1'b1:1'b0;



  assign byte_err_falling_w[6] = ((valid_1  == 1'b1) &&
                 (data_falling[55:48] != data_pattern_falling[55:48]))? 1'b1:1'b0;



  assign byte_err_falling_w[7] = ((valid_1  == 1'b1) &&
                 (data_falling[63:56] != data_pattern_falling[63:56]))? 1'b1:1'b0;



   
  assign byte_err_rising_w[0] =   ((valid_1   == 1'b1) &&
                 (data_rising[7:0] != data_pattern_rising[7:0]))? 1'b1 : 1'b0;



  assign byte_err_rising_w[1] =   ((valid_1   == 1'b1) &&
                 (data_rising[15:8] != data_pattern_rising[15:8]))? 1'b1 : 1'b0;



  assign byte_err_rising_w[2] =   ((valid_1   == 1'b1) &&
                 (data_rising[23:16] != data_pattern_rising[23:16]))? 1'b1 : 1'b0;



  assign byte_err_rising_w[3] =   ((valid_1   == 1'b1) &&
                 (data_rising[31:24] != data_pattern_rising[31:24]))? 1'b1 : 1'b0;



  assign byte_err_rising_w[4] =   ((valid_1   == 1'b1) &&
                 (data_rising[39:32] != data_pattern_rising[39:32]))? 1'b1 : 1'b0;



  assign byte_err_rising_w[5] =   ((valid_1   == 1'b1) &&
                 (data_rising[47:40] != data_pattern_rising[47:40]))? 1'b1 : 1'b0;



  assign byte_err_rising_w[6] =   ((valid_1   == 1'b1) &&
                 (data_rising[55:48] != data_pattern_rising[55:48]))? 1'b1 : 1'b0;



  assign byte_err_rising_w[7] =   ((valid_1   == 1'b1) &&
                 (data_rising[63:56] != data_pattern_rising[63:56]))? 1'b1 : 1'b0;



   assign byte_err_rising_a= |byte_err_rising[`data_width/8-1:0];
   assign byte_err_falling_a= |byte_err_falling[`data_width/8-1:0];

   always @ (posedge CLK)
     rst_r <= RESET;

   always @ (posedge CLK)
     begin
        byte_err_rising  <= byte_err_falling_w;
        byte_err_falling <= byte_err_rising_w;
     end

   always @ (posedge CLK)
     begin
        if (rst_r == 1'b1) begin
           rising_error  <= 1'b0;
           falling_error <= 1'b0;
           ERROR         <= 1'b0;
        end else begin
           rising_error  <= byte_err_rising_a;
           falling_error <= byte_err_falling_a;
           ERROR         <= rising_error || falling_error;
        end
     end

   always @ (posedge CLK)
     begin
        if (ERROR == 1'b1) begin
          //synthesis translate_off
           $display ("ERROR at time %t" , $time);
          //synthesis translate_on
        end
     end

   always @ (posedge CLK)
     begin
        if (rst_r == 1'b1)
          read_data_r <= `data_width*2'd0;

        else
          read_data_r <= READ_DATA_FIFO_OUT;
     end

   always @ (posedge CLK)
     begin
        if (rst_r == 1'b1) begin
           read_data_r2 <= `data_width*2'd0;
           write_data_r2 <= `data_width*2'd0;

        end else begin
           read_data_r2 <= read_data_r;
           write_data_r2 <= APP_COMPARE_DATA;
        end
     end

   always @ (posedge CLK)
     begin
        if (rst_r == 1'b1)
          begin
             valid   <= 1'b0;
             valid_1 <= 1'b0;
          end
        else
          begin
             valid   <= READ_DATA_VALID;
             valid_1 <= valid;
          end
     end

endmodule