?? mem_interface_top_top_0.txt
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///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : $Name: mig_v1_7 $
// \ \ Application : MIG
// / / Filename : mem_interface_top_top_0.v
// /___/ /\ Date Last Modified : $Date: 2007/02/15 12:06:16 $
// \ \ / \ Date Created : Mon May 2 2005
// \___\/\___\
//
// Device : Virtex-4
// Design Name : DDR SDRAM
// Description: Instantiates the main design logic of memory interface and
// interfaces with the user.
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
`include "../rtl/mem_interface_top_parameters_0.v"
module mem_interface_top_top_0
(
input clk_0,
input clk_90,
input sys_rst,
input sys_rst90,
input idelay_ctrl_rdy,
input [35:0] APP_AF_ADDR,
input APP_AF_WREN,
input [(`data_width*2)-1:0] APP_WDF_DATA,
input APP_WDF_WREN,
inout [`data_width-1:0] DDR_DQ,
inout [`data_strobe_width-1:0] DDR_DQS,
output DDR_RAS_N,
output DDR_CAS_N,
output DDR_WE_N,
output [`cke_width-1:0] DDR_CKE,
output [`no_of_cs-1:0] DDR_CS_N,
output[`data_mask_width-1:0] DDR_DM,
input [(`data_mask_width*2)-1:0] APP_MASK_DATA,
output [`bank_address-1:0] DDR_BA,
output [`row_address-1:0] DDR_A,
output [`clk_width-1:0] DDR_CK,
output [`clk_width-1:0] DDR_CK_N,
output CLK_TB,
output RESET_TB,
output init_done,
//test bench signals
output WDF_ALMOST_FULL,
output AF_ALMOST_FULL,
output [2:0] BURST_LENGTH,
output READ_DATA_VALID,
output [(`data_width*2)-1:0] READ_DATA_FIFO_OUT
);
wire [(`data_width*2)-1:0] wr_df_data;
wire [(`data_mask_width*2)-1:0] mask_df_data;
wire [`data_width-1:0] rd_data_rise ;
wire [`data_width-1:0] rd_data_fall ;
wire af_empty_w;
wire dq_tap_sel_done;
wire [35:0] af_addr;
wire ctrl_af_rden;
wire ctrl_wr_df_rden;
wire ctrl_dummy_rden;
wire ctrl_dqs_enable;
wire ctrl_dqs_reset;
wire ctrl_wr_en;
wire ctrl_rden;
wire [`ReadEnable-1:0] dqs_idelay_inc;
wire [`ReadEnable-1:0] dqs_idelay_ce;
wire [`ReadEnable-1:0] dqs_idelay_rst;
wire [`ReadEnable-1:0] data_idelay_inc;
wire [`ReadEnable-1:0] data_idelay_ce;
wire [`ReadEnable-1:0] data_idelay_rst;
wire wr_en;
wire dqs_rst;
wire dqs_en;
wire [`data_width-1:0] wr_data_rise;
wire [`data_width-1:0] wr_data_fall;
wire [`data_strobe_width-1:0] dqs_delayed;
wire [`data_mask_width-1:0] mask_data_fall;
wire [`data_mask_width-1:0] mask_data_rise;
wire [`row_address-1:0] ctrl_ddr_address;
wire [`bank_address-1:0] ctrl_ddr_ba;
wire ctrl_ddr_ras_L;
wire ctrl_ddr_cas_L;
wire ctrl_ddr_we_L;
wire [`no_of_cs-1:0] ctrl_ddr_cs_L;
wire [`cke_width-1:0] ctrl_ddr_cke;
wire dummy_write_pattern;
assign CLK_TB = clk_0;
assign RESET_TB = sys_rst;
mem_interface_top_data_path_0 data_path_00
(
.CLK (clk_0),
.CLK90 (clk_90),
.RESET0 (sys_rst),
.RESET90 (sys_rst90),
.idelay_ctrl_rdy (idelay_ctrl_rdy),
.CTRL_DUMMYREAD_START (ctrl_dummy_rden),
.dummy_write_pattern (dummy_write_pattern),
.WDF_DATA (wr_df_data),
.MASK_DATA (mask_df_data),
.CTRL_WREN (ctrl_wr_en),
.CTRL_DQS_RST (ctrl_dqs_reset),
.CTRL_DQS_EN (ctrl_dqs_enable),
.dqs_delayed (dqs_delayed),
.data_idelay_inc (data_idelay_inc),
.data_idelay_ce (data_idelay_ce),
.data_idelay_rst (data_idelay_rst),
.dqs_idelay_inc (dqs_idelay_inc),
.dqs_idelay_ce (dqs_idelay_ce),
.dqs_idelay_rst (dqs_idelay_rst),
.SEL_DONE (dq_tap_sel_done),
.dqs_rst (dqs_rst),
.dqs_en (dqs_en),
.wr_en (wr_en),
.wr_data_rise (wr_data_rise),
.wr_data_fall (wr_data_fall),
.mask_data_rise (mask_data_rise),
.mask_data_fall (mask_data_fall)
);
mem_interface_top_iobs_0 iobs_00
(
.DDR_CK (DDR_CK),
.DDR_CK_N (DDR_CK_N),
.CLK (clk_0),
.CLK90 (clk_90),
.RESET0 (sys_rst),
.RESET90 (sys_rst90),
.dqs_idelay_inc (dqs_idelay_inc),
.dqs_idelay_ce (dqs_idelay_ce),
.dqs_idelay_rst (dqs_idelay_rst),
.data_idelay_inc (data_idelay_inc),
.data_idelay_ce (data_idelay_ce),
.data_idelay_rst (data_idelay_rst),
.dqs_rst (dqs_rst),
.dqs_en (dqs_en),
.wr_en (wr_en),
.wr_data_rise (wr_data_rise),
.wr_data_fall (wr_data_fall),
.mask_data_rise (mask_data_rise),
.mask_data_fall (mask_data_fall),
.rd_data_rise (rd_data_rise),
.rd_data_fall (rd_data_fall),
.dqs_delayed (dqs_delayed),
.DDR_DQ (DDR_DQ),
.DDR_DQS (DDR_DQS),
.DDR_DM (DDR_DM),
.ctrl_ddr_address (ctrl_ddr_address),
.ctrl_ddr_ba (ctrl_ddr_ba),
.ctrl_ddr_ras_L (ctrl_ddr_ras_L),
.ctrl_ddr_cas_L (ctrl_ddr_cas_L),
.ctrl_ddr_we_L (ctrl_ddr_we_L),
.ctrl_ddr_cs_L (ctrl_ddr_cs_L),
.ctrl_ddr_cke (ctrl_ddr_cke),
.DDR_ADDRESS (DDR_A),
.DDR_BA (DDR_BA),
.DDR_RAS_L (DDR_RAS_N),
.DDR_CAS_L (DDR_CAS_N),
.DDR_WE_L (DDR_WE_N),
.DDR_CKE (DDR_CKE),
.ddr_cs_L (DDR_CS_N)
);
mem_interface_top_user_interface_0 user_interface_00
(
.CLK (clk_0),
.clk90 (clk_90),
.RESET (sys_rst),
.ctrl_rden (ctrl_rden),
.READ_DATA_RISE (rd_data_rise),
.READ_DATA_FALL (rd_data_fall),
.READ_DATA_FIFO_OUT (READ_DATA_FIFO_OUT),
.READ_DATA_VALID (READ_DATA_VALID),
.AF_EMPTY (af_empty_w),
.AF_ALMOST_FULL (AF_ALMOST_FULL),
.APP_AF_ADDR (APP_AF_ADDR),
.APP_AF_WREN (APP_AF_WREN),
.CTRL_AF_RDEN (ctrl_af_rden),
.AF_ADDR (af_addr),
.APP_WDF_DATA (APP_WDF_DATA),
.APP_MASK_DATA (APP_MASK_DATA),
.APP_WDF_WREN (APP_WDF_WREN),
.CTRL_WDF_RDEN (ctrl_wr_df_rden),
.comp_done (comp_done),
.WDF_DATA (wr_df_data),
.MASK_DATA (mask_df_data),
.WDF_ALMOST_FULL (WDF_ALMOST_FULL)
);
mem_interface_top_ddr_controller_0 ddr_controller_00
(
.clk_0 (clk_0),
.rst (sys_rst),
.burst_length (BURST_LENGTH),
.af_addr (af_addr),
.af_empty (af_empty_w),
.comp_done (comp_done),
.phy_Dly_Slct_Done (dq_tap_sel_done),
.ctrl_Dummyread_Start (ctrl_dummy_rden),
.dummy_write_pattern (dummy_write_pattern),
.ctrl_af_RdEn (ctrl_af_rden),
.ctrl_Wdf_RdEn (ctrl_wr_df_rden),
.ctrl_Dqs_Rst (ctrl_dqs_reset),
.ctrl_Dqs_En (ctrl_dqs_enable),
.ctrl_WrEn (ctrl_wr_en),
.ctrl_RdEn (ctrl_rden),
.ctrl_ddr_address (ctrl_ddr_address),
.ctrl_ddr_ba (ctrl_ddr_ba),
.ctrl_ddr_ras_L (ctrl_ddr_ras_L),
.ctrl_ddr_cas_L (ctrl_ddr_cas_L),
.ctrl_ddr_we_L (ctrl_ddr_we_L),
.ctrl_ddr_cs_L (ctrl_ddr_cs_L),
.ctrl_ddr_cke (ctrl_ddr_cke),
.init_done (init_done)
);
endmodule
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