?? mem_interface_top_data_path_iobs_0.txt
字號:
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[0]),
.DATA_DLYCE (data_idelay_ce[0]),
.DATA_DLYRST (data_idelay_rst[0]),
.WRITE_DATA_RISE (wr_data_rise[25]),
.WRITE_DATA_FALL (wr_data_fall[25]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[25]),
.READ_DATA_RISE (rd_data_rise[25]),
.READ_DATA_FALL (rd_data_fall[25])
);
mem_interface_top_v4_dq_iob v4_dq_iob26
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[0]),
.DATA_DLYCE (data_idelay_ce[0]),
.DATA_DLYRST (data_idelay_rst[0]),
.WRITE_DATA_RISE (wr_data_rise[26]),
.WRITE_DATA_FALL (wr_data_fall[26]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[26]),
.READ_DATA_RISE (rd_data_rise[26]),
.READ_DATA_FALL (rd_data_fall[26])
);
mem_interface_top_v4_dq_iob v4_dq_iob27
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[0]),
.DATA_DLYCE (data_idelay_ce[0]),
.DATA_DLYRST (data_idelay_rst[0]),
.WRITE_DATA_RISE (wr_data_rise[27]),
.WRITE_DATA_FALL (wr_data_fall[27]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[27]),
.READ_DATA_RISE (rd_data_rise[27]),
.READ_DATA_FALL (rd_data_fall[27])
);
mem_interface_top_v4_dq_iob v4_dq_iob28
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[0]),
.DATA_DLYCE (data_idelay_ce[0]),
.DATA_DLYRST (data_idelay_rst[0]),
.WRITE_DATA_RISE (wr_data_rise[28]),
.WRITE_DATA_FALL (wr_data_fall[28]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[28]),
.READ_DATA_RISE (rd_data_rise[28]),
.READ_DATA_FALL (rd_data_fall[28])
);
mem_interface_top_v4_dq_iob v4_dq_iob29
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[0]),
.DATA_DLYCE (data_idelay_ce[0]),
.DATA_DLYRST (data_idelay_rst[0]),
.WRITE_DATA_RISE (wr_data_rise[29]),
.WRITE_DATA_FALL (wr_data_fall[29]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[29]),
.READ_DATA_RISE (rd_data_rise[29]),
.READ_DATA_FALL (rd_data_fall[29])
);
mem_interface_top_v4_dq_iob v4_dq_iob30
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[0]),
.DATA_DLYCE (data_idelay_ce[0]),
.DATA_DLYRST (data_idelay_rst[0]),
.WRITE_DATA_RISE (wr_data_rise[30]),
.WRITE_DATA_FALL (wr_data_fall[30]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[30]),
.READ_DATA_RISE (rd_data_rise[30]),
.READ_DATA_FALL (rd_data_fall[30])
);
mem_interface_top_v4_dq_iob v4_dq_iob31
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[0]),
.DATA_DLYCE (data_idelay_ce[0]),
.DATA_DLYRST (data_idelay_rst[0]),
.WRITE_DATA_RISE (wr_data_rise[31]),
.WRITE_DATA_FALL (wr_data_fall[31]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[31]),
.READ_DATA_RISE (rd_data_rise[31]),
.READ_DATA_FALL (rd_data_fall[31])
);
mem_interface_top_v4_dq_iob v4_dq_iob32
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[1]),
.DATA_DLYCE (data_idelay_ce[1]),
.DATA_DLYRST (data_idelay_rst[1]),
.WRITE_DATA_RISE (wr_data_rise[32]),
.WRITE_DATA_FALL (wr_data_fall[32]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[32]),
.READ_DATA_RISE (rd_data_rise[32]),
.READ_DATA_FALL (rd_data_fall[32])
);
mem_interface_top_v4_dq_iob v4_dq_iob33
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[1]),
.DATA_DLYCE (data_idelay_ce[1]),
.DATA_DLYRST (data_idelay_rst[1]),
.WRITE_DATA_RISE (wr_data_rise[33]),
.WRITE_DATA_FALL (wr_data_fall[33]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[33]),
.READ_DATA_RISE (rd_data_rise[33]),
.READ_DATA_FALL (rd_data_fall[33])
);
mem_interface_top_v4_dq_iob v4_dq_iob34
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[1]),
.DATA_DLYCE (data_idelay_ce[1]),
.DATA_DLYRST (data_idelay_rst[1]),
.WRITE_DATA_RISE (wr_data_rise[34]),
.WRITE_DATA_FALL (wr_data_fall[34]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[34]),
.READ_DATA_RISE (rd_data_rise[34]),
.READ_DATA_FALL (rd_data_fall[34])
);
mem_interface_top_v4_dq_iob v4_dq_iob35
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[1]),
.DATA_DLYCE (data_idelay_ce[1]),
.DATA_DLYRST (data_idelay_rst[1]),
.WRITE_DATA_RISE (wr_data_rise[35]),
.WRITE_DATA_FALL (wr_data_fall[35]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[35]),
.READ_DATA_RISE (rd_data_rise[35]),
.READ_DATA_FALL (rd_data_fall[35])
);
mem_interface_top_v4_dq_iob v4_dq_iob36
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[1]),
.DATA_DLYCE (data_idelay_ce[1]),
.DATA_DLYRST (data_idelay_rst[1]),
.WRITE_DATA_RISE (wr_data_rise[36]),
.WRITE_DATA_FALL (wr_data_fall[36]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[36]),
.READ_DATA_RISE (rd_data_rise[36]),
.READ_DATA_FALL (rd_data_fall[36])
);
mem_interface_top_v4_dq_iob v4_dq_iob37
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[1]),
.DATA_DLYCE (data_idelay_ce[1]),
.DATA_DLYRST (data_idelay_rst[1]),
.WRITE_DATA_RISE (wr_data_rise[37]),
.WRITE_DATA_FALL (wr_data_fall[37]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[37]),
.READ_DATA_RISE (rd_data_rise[37]),
.READ_DATA_FALL (rd_data_fall[37])
);
mem_interface_top_v4_dq_iob v4_dq_iob38
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[1]),
.DATA_DLYCE (data_idelay_ce[1]),
.DATA_DLYRST (data_idelay_rst[1]),
.WRITE_DATA_RISE (wr_data_rise[38]),
.WRITE_DATA_FALL (wr_data_fall[38]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[38]),
.READ_DATA_RISE (rd_data_rise[38]),
.READ_DATA_FALL (rd_data_fall[38])
);
mem_interface_top_v4_dq_iob v4_dq_iob39
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[1]),
.DATA_DLYCE (data_idelay_ce[1]),
.DATA_DLYRST (data_idelay_rst[1]),
.WRITE_DATA_RISE (wr_data_rise[39]),
.WRITE_DATA_FALL (wr_data_fall[39]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[39]),
.READ_DATA_RISE (rd_data_rise[39]),
.READ_DATA_FALL (rd_data_fall[39])
);
mem_interface_top_v4_dq_iob v4_dq_iob40
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[1]),
.DATA_DLYCE (data_idelay_ce[1]),
.DATA_DLYRST (data_idelay_rst[1]),
.WRITE_DATA_RISE (wr_data_rise[40]),
.WRITE_DATA_FALL (wr_data_fall[40]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[40]),
.READ_DATA_RISE (rd_data_rise[40]),
.READ_DATA_FALL (rd_data_fall[40])
);
mem_interface_top_v4_dq_iob v4_dq_iob41
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[1]),
.DATA_DLYCE (data_idelay_ce[1]),
.DATA_DLYRST (data_idelay_rst[1]),
.WRITE_DATA_RISE (wr_data_rise[41]),
.WRITE_DATA_FALL (wr_data_fall[41]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[41]),
.READ_DATA_RISE (rd_data_rise[41]),
.READ_DATA_FALL (rd_data_fall[41])
);
mem_interface_top_v4_dq_iob v4_dq_iob42
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[1]),
.DATA_DLYCE (data_idelay_ce[1]),
.DATA_DLYRST (data_idelay_rst[1]),
.WRITE_DATA_RISE (wr_data_rise[42]),
.WRITE_DATA_FALL (wr_data_fall[42]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[42]),
.READ_DATA_RISE (rd_data_rise[42]),
.READ_DATA_FALL (rd_data_fall[42])
);
mem_interface_top_v4_dq_iob v4_dq_iob43
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[1]),
.DATA_DLYCE (data_idelay_ce[1]),
.DATA_DLYRST (data_idelay_rst[1]),
.WRITE_DATA_RISE (wr_data_rise[43]),
.WRITE_DATA_FALL (wr_data_fall[43]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[43]),
.READ_DATA_RISE (rd_data_rise[43]),
.READ_DATA_FALL (rd_data_fall[43])
);
mem_interface_top_v4_dq_iob v4_dq_iob44
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[1]),
.DATA_DLYCE (data_idelay_ce[1]),
.DATA_DLYRST (data_idelay_rst[1]),
.WRITE_DATA_RISE (wr_data_rise[44]),
.WRITE_DATA_FALL (wr_data_fall[44]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[44]),
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