///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor             : Xilinx
// \   \   \/    Version            : $Name: mig_v1_7 $
//  \   \        Application        : MIG
//  /   /        Filename           : mem_interface_top.v
// /___/   /\    Date Last Modified : $Date: 2007/02/19 05:41:10 $
// \   \  /  \   Date Created       : Mon May 2 2005
//  \___\/\___\
//
// Device      : Virtex-4
// Design Name : DDR SDRAM
//Description     : This module is the top most module which interfaces with
//                        the system and the memory.
///////////////////////////////////////////////////////////////////////////////


`timescale 1ns / 1ps


module mem_interface_top
  (
   inout [63:0] cntrl0_DDR_DQ,
   output [11:0] cntrl0_DDR_A,
   output [1:0] cntrl0_DDR_BA,
   output  cntrl0_DDR_CKE,
   output  cntrl0_DDR_CS_N,
   output  cntrl0_DDR_RAS_N,
   output  cntrl0_DDR_CAS_N,
   output  cntrl0_DDR_WE_N,
   output [7:0] cntrl0_DDR_DM,
   input  SYS_CLK_P,
   input  SYS_CLK_N,
   input  CLK200_P,
   input  CLK200_N,
   output  cntrl0_ERROR,
   output  init_done,
   input  SYS_RESET_IN_N,
   inout [7:0] cntrl0_DDR_DQS,
   output [3:0] cntrl0_DDR_CK,
   output [3:0] cntrl0_DDR_CK_N
   );

   wire clk_0;
   wire clk_90;
   wire clk_200;
   wire sys_rst;
   wire sys_rst90;
   wire sys_rst_r1;
   wire idelay_ctrl_rdy;

   mem_interface_top_main_0     main_00
   (
   .DDR_DQ	(cntrl0_DDR_DQ),
   .DDR_A	(cntrl0_DDR_A),
   .DDR_BA	(cntrl0_DDR_BA),
   .DDR_CKE	(cntrl0_DDR_CKE),
   .DDR_CS_N	(cntrl0_DDR_CS_N),
   .DDR_RAS_N	(cntrl0_DDR_RAS_N),
   .DDR_CAS_N	(cntrl0_DDR_CAS_N),
   .DDR_WE_N	(cntrl0_DDR_WE_N),
   .DDR_DM	(cntrl0_DDR_DM),
   .ERROR	(cntrl0_ERROR),
   .init_done	(init_done),
   .DDR_DQS	(cntrl0_DDR_DQS),
   .DDR_CK	(cntrl0_DDR_CK),
   .DDR_CK_N	(cntrl0_DDR_CK_N),
   
   .clk_0             (clk_0),
   .clk_90            (clk_90),
   .idelay_ctrl_rdy   (idelay_ctrl_rdy),
   .sys_rst           (sys_rst),
   .sys_rst90         (sys_rst90)
   );


   mem_interface_top_infrastructure infrastructure0
       (
        .CLK               (clk_0),
        .CLK90             (clk_90),
        .CLK200            (clk_200),
        .sys_rst           (sys_rst),
        .sys_rst90         (sys_rst90),
        .sys_rst_r1        (sys_rst_r1),
        .idelay_ctrl_rdy   (idelay_ctrl_rdy),
    .SYS_CLK_P	(SYS_CLK_P),
    .SYS_CLK_N	(SYS_CLK_N),
    .CLK200_P	(CLK200_P),
    .CLK200_N	(CLK200_N),
    .SYS_RESET_IN_N	(SYS_RESET_IN_N)
        );

   mem_interface_top_idelay_ctrl idelay_ctrl0
     (
      .CLK200     (clk_200),
      .RESET      (sys_rst_r1),
      .RDY_STATUS (idelay_ctrl_rdy)
      );

endmodule