///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor             : Xilinx
// \   \   \/    Version            : $Name: mig_v1_7 $
//  \   \        Application        : MIG
//  /   /        Filename           : mem_interface_top_idelay_ctrl.v
// /___/   /\    Date Last Modified : $Date: 2007/02/15 12:06:16 $
// \   \  /  \   Date Created       : Mon May 2 2005
//  \___\/\___\
//
// Device      : Virtex-4
// Design Name : DDR SDRAM
// Description: Instantaites the IDELAYCTRL primitive of the Virtex4 device
//              which continously calibrates the IDELAY elements in the
//              region in case of varying operating conditions. It takes
//              a 200MHz clock as an input.
///////////////////////////////////////////////////////////////////////////////

`timescale 1ns / 1ps

module mem_interface_top_idelay_ctrl
  (
   input        CLK200,
   input        RESET,
   output       RDY_STATUS
   );


   IDELAYCTRL idelayctrl0
     (
      .RDY(RDY_STATUS),
      .REFCLK(CLK200),
      .RST(RESET)
      );

endmodule