///////////////////////////////////////////////////////////////////////////////// Copyright (c) 2005 Xilinx, Inc.// This design is confidential and proprietary of Xilinx, All Rights Reserved./////////////////////////////////////////////////////////////////////////////////   ____  ____//  /   /\/   /// /___/  \  /   Vendor             : Xilinx// \   \   \/    Version            : $Name: mig_v1_7 $//  \   \        Application        : MIG//  /   /        Filename           : mem_interface_top_infrastructure.v// /___/   /\    Date Last Modified : $Date: 2007/02/15 12:06:16 $// \   \  /  \   Date Created       : Mon May 2 2005//  \___\/\___\//// Device      : Virtex-4// Design Name : DDR SDRAM// Description: Instantiates the DCM of the FPGA device. The system clock is//              given as the input and two clocks that are phase shifted by//              90 degrees are taken out. It also give the reset signals in//              phase with the clocks.///////////////////////////////////////////////////////////////////////////////`timescale 1ns / 1ps`include "../rtl/mem_interface_top_parameters_0.v"module mem_interface_top_infrastructure  (   input        SYS_CLK_N,input        SYS_CLK_P,input        CLK200_N,input        CLK200_P,input        SYS_RESET_IN_N,//active-lowinput        idelay_ctrl_rdy,  output       CLK,output       CLK90,output       CLK200,output       sys_rst,output       sys_rst90,output       sys_rst_rl   );   wire         clk0_bufg_in;wire         clk90_bufg_in;wire         clk0_bufg_out;wire         clk90_bufg_out;wire         clk0_bufg1_out;wire         REF_CLK200_IN;wire         LOCKED;   wire         SYS_CLK_IN ;      localparam RST_SYNC_NUM = 12;   reg [RST_SYNC_NUM-1:0] rst0_sync_r;   reg [RST_SYNC_NUM-1:0] rst200_sync_r;   reg [RST_SYNC_NUM-1:0] rst90_sync_r;   wire                   SYS_RESET;   wire                   rst_tmp;     assign CLK         = clk0_bufg_out;  assign CLK90       = clk90_bufg_out;  assign CLK200      = clk0_bufg1_out;   assign SYS_RESET   = `reset_active_low ? ~SYS_RESET_IN_N : SYS_RESET_IN_N;   IBUFGDS_LVPECL_25  lvds_sys_clk_input   (    .I (SYS_CLK_P),    .IB(SYS_CLK_N),    .O (SYS_CLK_IN)  );IBUFGDS_LVPECL_25 lvpecl_clk200_in   (    .O(REF_CLK200_IN),    .I(CLK200_P),    .IB(CLK200_N)  );  defparam DCM_BASE0.DLL_FREQUENCY_MODE = "HIGH";defparam DCM_BASE0.DUTY_CYCLE_CORRECTION = "TRUE";defparam DCM_BASE0.CLKDV_DIVIDE = 16.0;defparam DCM_BASE0.CLKFX_MULTIPLY = 2;defparam DCM_BASE0.CLKFX_DIVIDE = 8;defparam DCM_BASE0.FACTORY_JF = 16'hF0F0;defparam DCM_BASE0.DCM_PERFORMANCE_MODE = "MAX_SPEED";DCM_BASE DCM_BASE0 (                .CLK0(clk0_bufg_in),                .CLK180(),                .CLK270(),                .CLK2X(),                .CLK2X180(),                .CLK90(clk90_bufg_in),                .CLKDV(),                .CLKFX(),                .CLKFX180(),                .LOCKED(LOCKED),                .CLKFB(clk0_bufg_out),                .CLKIN(SYS_CLK_IN),                .RST(SYS_RESET)                  );     BUFG dcm_clk0     (      .O(clk0_bufg_out),      .I(clk0_bufg_in)    );  BUFG dcm_clk90     (      .O(clk90_bufg_out),      .I(clk90_bufg_in)    );  BUFG dcm1_clk0     (      .O(clk0_bufg1_out),      .I(REF_CLK200_IN)    );  assign rst_tmp = ~LOCKED | ~idelay_ctrl_rdy | SYS_RESET;  always @(posedge CLK or posedge rst_tmp)    if (rst_tmp)      rst0_sync_r <= {RST_SYNC_NUM{1'b1}};    else      // logical left shift by one (pads with 0)      rst0_sync_r <= rst0_sync_r << 1;  always @(posedge CLK90 or posedge rst_tmp)    if (rst_tmp)      rst90_sync_r <= {RST_SYNC_NUM{1'b1}};    else      rst90_sync_r <= rst90_sync_r << 1;  // make sure CLK200 doesn't depend on IDELAY_CTRL_RDY, else chicken n' egg  always @(posedge CLK200 or negedge LOCKED)    if (!LOCKED)      rst200_sync_r <= {RST_SYNC_NUM{1'b1}};    else      rst200_sync_r <= rst200_sync_r << 1;  assign sys_rst    = rst0_sync_r[RST_SYNC_NUM-1];  assign sys_rst90  = rst90_sync_r[RST_SYNC_NUM-1];  assign sys_rst_r1 = rst200_sync_r[RST_SYNC_NUM-1];endmodule