BlockType		  Reference	  Name			  "inter_deinterleaving"	  Ports			  [2, 2, 0, 0, 0]	  Position		  [550, 769, 695, 891]	  Orientation		  "left"	  ForegroundColor	  "blue"	  NamePlacement		  "alternate"	  SourceBlock		  "utra_lib/Modulation  blocks/dl_RX_demodulat""ion/inter_deinterleaving"	  SourceType		  ""	  Int_mode		  "Inter_int_mode"	  bits_in_frame		  "bits_in_frame"	  nFrames		  "nFrames"	  cols			  "cols"	}	Block {	  BlockType		  Reference	  Name			  "inter_interleaving"	  Ports			  [1, 1, 0, 0, 0]	  Position		  [555, 109, 685, 201]	  ForegroundColor	  "blue"	  SourceBlock		  "utra_lib/Modulation  blocks/dl_TX_modulatio""n/inter_interleaving"	  SourceType		  ""	  Int_mode		  "Inter_int_mode"	  bits_in_frame		  "bits_in_frame"	  nFrames		  "nFrames"	  cols			  "cols"	}	Block {	  BlockType		  Reference	  Name			  "intra_deinterleaving"	  Ports			  [2, 2, 0, 0, 0]	  Position		  [735, 771, 885, 889]	  Orientation		  "left"	  ForegroundColor	  "blue"	  NamePlacement		  "alternate"	  SourceBlock		  "utra_lib/Modulation  blocks/dl_RX_demodulat""ion/intra_deinterleaving"	  SourceType		  ""	  Int_mode		  "Intra_int_flag"	  bits_in_frame		  "bits_in_frame"	  nFrames		  "nFrames"	}	Block {	  BlockType		  Reference	  Name			  "intra_interleaving"	  Ports			  [1, 1, 0, 0, 0]	  Position		  [725, 109, 855, 201]	  ForegroundColor	  "blue"	  SourceBlock		  "utra_lib/Modulation  blocks/dl_TX_modulatio""n/intra_interleaving"	  SourceType		  ""	  Int_mode		  "Intra_int_flag"	  bits_in_frame		  "bits_in_frame"	  nFrames		  "nFrames"	  nSlots		  "nSlot"	}	Block {	  BlockType		  Reference	  Name			  "rate_dematching"	  Ports			  [2, 2, 0, 0, 0]	  Position		  [420, 771, 520, 889]	  Orientation		  "left"	  ForegroundColor	  "green"	  NamePlacement		  "alternate"	  FontName		  "helvetica"	  FontSize		  12	  FontWeight		  "bold"	  SourceBlock		  "utra_lib/Channel coding block/dl_RX_channel""_decoding/rate_dematching"	  SourceType		  ""	  dr_in			  "nFrames*bits_in_frame"	  dr_out		  "K*(N+nCRC)+nTail"	  punk			  "0.2"	  nFrames		  "nFrames"	}	Block {	  BlockType		  Reference	  Name			  "remove CRC"	  Ports			  [2, 2, 0, 0, 0]	  Position		  [65, 768, 200, 892]	  Orientation		  "left"	  ForegroundColor	  "green"	  NamePlacement		  "alternate"	  FontName		  "helvetica"	  FontSize		  12	  FontWeight		  "bold"	  SourceBlock		  "utra_lib/Channel coding block/dl_RX_channel""_decoding/remove CRC"	  SourceType		  ""	  nReCRC		  "N+nCRC"	  nCRC			  "nCRC"	  crc_poly		  "crc_poly"	  nFrames		  "nFrames"	}	Block {	  BlockType		  Reference	  Name			  "spreading"	  Ports			  [1, 1, 0, 0, 0]	  Position		  [895, 122, 1030, 188]	  SourceBlock		  "utra_lib/Modulation  blocks/spreading"	  SourceType		  ""	  N			  "bits_in_frame/nSlot"	  C			  "CD"	  nSlot			  "nSlot"	}	Block {	  BlockType		  Reference	  Name			  "spreading1"	  Ports			  [1, 1, 0, 0, 0]	  Position		  [905, 272, 1045, 338]	  SourceBlock		  "utra_lib/Modulation  blocks/spreading"	  SourceType		  ""	  N			  "sum(control)"	  C			  "CC"	  nSlot			  "nSlot"	}	Block {	  BlockType		  Mux	  Name			  "tail_mux"	  Ports			  [2, 1, 0, 0, 0]	  Position		  [390, 105, 395, 205]	  ShowName		  off	  FontName		  "helvetica"	  FontSize		  12	  Inputs		  "2"	  DisplayOption		  "bar"	}	Block {	  BlockType		  Reference	  Name			  "ul_rake"	  Ports			  [5, 4, 0, 0, 0]	  Position		  [1056, 605, 1214, 795]	  Orientation		  "down"	  NamePlacement		  "alternate"	  FontName		  "helvetica"	  FontSize		  12	  SourceBlock		  "utra_lib/Receivers/ul_rake"	  SourceType		  ""	  N_rake		  "chips_in_slot"	  nSlot			  "nSlot"	  nPilot		  "nPilot"	  th			  "0.1"	  nFin			  "1"	  CD			  "CD"	  CC			  "CC"	}	Line {	  SrcBlock		  "intra_interleaving"	  SrcPort		  1	  DstBlock		  "spreading"	  DstPort		  1	}	Line {	  SrcBlock		  "Rate Matching"	  SrcPort		  1	  DstBlock		  "inter_interleaving"	  DstPort		  1	}	Line {	  SrcBlock		  "Constant"	  SrcPort		  1	  DstBlock		  "ch_coding"	  DstPort		  2	}	Line {	  SrcBlock		  "Add CRC2"	  SrcPort		  1	  DstBlock		  "ch_coding"	  DstPort		  1	}	Line {	  SrcBlock		  "ch_coding"	  SrcPort		  1	  DstBlock		  "tail_mux"	  DstPort		  1	}	Line {	  SrcBlock		  "ch_coding"	  SrcPort		  2	  DstBlock		  "tail_mux"	  DstPort		  2	}	Line {	  SrcBlock		  "tail_mux"	  SrcPort		  1	  DstBlock		  "Rate Matching"	  DstPort		  1	}	Line {	  SrcBlock		  "data source 01 ..10"	  SrcPort		  1	  Points		  [0, 55]	  Branch {	    Points		    [0, 5]	    DstBlock		    "Add CRC2"	    DstPort		    1	  }	  Branch {	    Points		    [0, 275]	    DstBlock		    "Delayed ber calculation"	    DstPort		    1	  }	}	Line {	  SrcBlock		  "inter_interleaving"	  SrcPort		  1	  DstBlock		  "intra_interleaving"	  DstPort		  1	}	Line {	  SrcBlock		  "control channel bits"	  SrcPort		  1	  DstBlock		  "spreading1"	  DstPort		  1	}	Line {	  SrcBlock		  "spreading1"	  SrcPort		  1	  DstBlock		  "channel2"	  DstPort		  2	}	Line {	  SrcBlock		  "spreading"	  SrcPort		  1	  Points		  [60, 0]	  DstBlock		  "channel2"	  DstPort		  1	}	Line {	  SrcBlock		  "channel2"	  SrcPort		  2	  DstBlock		  "Channel estimator"	  DstPort		  1	}	Line {	  SrcBlock		  "channel2"	  SrcPort		  3	  DstBlock		  "Channel estimator"	  DstPort		  2	}	Line {	  SrcBlock		  "channel2"	  SrcPort		  1	  DstBlock		  "ul_rake"	  DstPort		  1	}	Line {	  SrcBlock		  "Channel estimator"	  SrcPort		  1	  Points		  [0, 5]	  DstBlock		  "ul_rake"	  DstPort		  2	}	Line {	  SrcBlock		  "Channel estimator"	  SrcPort		  2	  DstBlock		  "ul_rake"	  DstPort		  3	}	Line {	  SrcBlock		  "Channel estimator"	  SrcPort		  3	  Points		  [0, 5]	  DstBlock		  "ul_rake"	  DstPort		  4	}	Line {	  SrcBlock		  "channel2"	  SrcPort		  4	  DstBlock		  "ul_rake"	  DstPort		  5	}	Line {	  SrcBlock		  "Buffer"	  SrcPort		  2	  Points		  [-20, 0]	  DstBlock		  "intra_deinterleaving"	  DstPort		  2	}	Line {	  SrcBlock		  "Buffer"	  SrcPort		  1	  DstBlock		  "intra_deinterleaving"	  DstPort		  1	}	Line {	  SrcBlock		  "intra_deinterleaving"	  SrcPort		  1	  DstBlock		  "inter_deinterleaving"	  DstPort		  1	}	Line {	  SrcBlock		  "intra_deinterleaving"	  SrcPort		  2	  DstBlock		  "inter_deinterleaving"	  DstPort		  2	}	Line {	  SrcBlock		  "ul_rake"	  SrcPort		  1	  DstBlock		  "Buffer"	  DstPort		  1	}	Line {	  SrcBlock		  "ul_rake"	  SrcPort		  2	  Points		  [0, 40]	  DstBlock		  "Buffer"	  DstPort		  2	}	Line {	  SrcBlock		  "inter_deinterleaving"	  SrcPort		  1	  DstBlock		  "rate_dematching"	  DstPort		  1	}	Line {	  SrcBlock		  "ch_decoding"	  SrcPort		  1	  DstBlock		  "remove CRC"	  DstPort		  1	}	Line {	  SrcBlock		  "ch_decoding"	  SrcPort		  2	  DstBlock		  "remove CRC"	  DstPort		  2	}	Line {	  SrcBlock		  "rate_dematching"	  SrcPort		  1	  DstBlock		  "ch_decoding"	  DstPort		  1	}	Line {	  SrcBlock		  "rate_dematching"	  SrcPort		  2	  DstBlock		  "ch_decoding"	  DstPort		  2	}	Line {	  SrcBlock		  "inter_deinterleaving"	  SrcPort		  2	  DstBlock		  "rate_dematching"	  DstPort		  2	}	Line {	  SrcBlock		  "remove CRC"	  SrcPort		  2	  DstBlock		  "To Workspace24"	  DstPort		  1	}	Line {	  SrcBlock		  "remove CRC"	  SrcPort		  1	  Points		  [-20, 0; 0, -350]	  DstBlock		  "Delayed ber calculation"	  DstPort		  2	}	Line {	  SrcBlock		  "Delayed ber calculation"	  SrcPort		  1	  Points		  [45, 0]	  Branch {	    DstBlock		    "To Workspace23"	    DstPort		    1	  }	  Branch {	    DstBlock		    "Display1"	    DstPort		    1	  }	}	Annotation {	  Position		  [195, 47]	  Text			  "N = input block size"	}	Annotation {	  Position		  [507, 787]	  Text			  "\n\n\n"	}      }    }  }}