library verilog;use verilog.vl_types.all;entity smbus_controller is    port(        address_in_ext  : in     vl_logic_vector(7 downto 0);        data_in         : inout  vl_logic_vector(7 downto 0);        chipselect      : in     vl_logic;        busy_bus_ext    : out    vl_logic;        irq_ext         : out    vl_logic;        read_ext        : in     vl_logic;        write_ext       : in     vl_logic;        sda             : inout  vl_logic;        scl             : inout  vl_logic;        reset_ext       : in     vl_logic    );end smbus_controller;