?? _primary.vhd
字號:
library verilog;use verilog.vl_types.all;entity arbitration is port( reset : in vl_logic; clk : in vl_logic; sda : in vl_logic; scl : in vl_logic; arbt_failed : out vl_logic; temp_7 : in vl_logic; enable : in vl_logic; ack_slave : in vl_logic; nack_slave : in vl_logic );end arbitration;
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