library verilog;use verilog.vl_types.all;entity clkgen_low_extend_detect is    port(        reset           : in     vl_logic;        scl             : in     vl_logic;        enable          : in     vl_logic;        clk             : in     vl_logic;        ctrl_w          : out    vl_logic;        count           : out    vl_logic_vector(5 downto 0);        wait1           : in     vl_logic    );end clkgen_low_extend_detect;