volatile PPSGSTR _PPSG;                                    /* Port G Polarity Select Register */
volatile PPSHSTR _PPSH;                                    /* Port H Polarity Select Register */
volatile PPSJSTR _PPSJ;                                    /* PortJP Polarity Select Register */
volatile PPSLSTR _PPSL;                                    /* Port L Polarity Select Register */
volatile PPSSSTR _PPSS;                                    /* Port S Polarity Select Register */
volatile PPSTSTR _PPST;                                    /* Port T Polarity Select Register */
volatile PTGSTR _PTG;                                      /* Port G I/O Register */
volatile PTHSTR _PTH;                                      /* Port H I/O Register */
volatile PTIGSTR _PTIG;                                    /* Port G Input */
volatile PTIHSTR _PTIH;                                    /* Port H Input Register */
volatile PTIJSTR _PTIJ;                                    /* Port J Input Register */
volatile PTILSTR _PTIL;                                    /* Port L Input */
volatile PTISSTR _PTIS;                                    /* Port S Input */
volatile PTITSTR _PTIT;                                    /* Port T Input */
volatile PTJSTR _PTJ;                                      /* Port J I/O Register */
volatile PTLSTR _PTL;                                      /* Port L I/O Register */
volatile PTSSTR _PTS;                                      /* Port S I/O Register */
volatile PTTSTR _PTT;                                      /* Port T I/O Register */
volatile PUCRSTR _PUCR;                                    /* Pull-Up Control Register */
volatile RDRGSTR _RDRG;                                    /* Port G Reduced Drive Register */
volatile RDRHSTR _RDRH;                                    /* Port H Reduced Drive Register */
volatile RDRIVSTR _RDRIV;                                  /* Reduced Drive of I/O Lines */
volatile RDRJSTR _RDRJ;                                    /* Port J Reduced Drive Register */
volatile RDRLSTR _RDRL;                                    /* Port L Reduced Drive Register */
volatile RDRSSTR _RDRS;                                    /* Port S Reduced Drive Register */
volatile RDRTSTR _RDRT;                                    /* Port T Reduced Drive Register */
volatile REFDVSTR _REFDV;                                  /* CRG Reference Divider Register */
volatile RTICTLSTR _RTICTL;                                /* CRG RTI Control Register */
volatile RXCTSSTR _RXCTS;                                  /* Receive Control and Status */
volatile SCI0CR1STR _SCI0CR1;                              /* SCI 0 Control Register 1 */
volatile SCI0CR2STR _SCI0CR2;                              /* SCI 0 Control Register 2 */
volatile SCI0DRHSTR _SCI0DRH;                              /* SCI 0 Data Register High */
volatile SCI0DRLSTR _SCI0DRL;                              /* SCI 0 Data Register Lw */
volatile SCI0SR1STR _SCI0SR1;                              /* SCI 0 Status Register 1 */
volatile SCI0SR2STR _SCI0SR2;                              /* SCI 0 Status Register 2 */
volatile SCI1CR1STR _SCI1CR1;                              /* SCI 1 Control Register 1 */
volatile SCI1CR2STR _SCI1CR2;                              /* SCI 1 Control Register 2 */
volatile SCI1DRHSTR _SCI1DRH;                              /* SCI 1 Data Register High */
volatile SCI1DRLSTR _SCI1DRL;                              /* SCI 1 Data Register Lw */
volatile SCI1SR1STR _SCI1SR1;                              /* SCI 1 Status Register 1 */
volatile SCI1SR2STR _SCI1SR2;                              /* SCI 1 Status Register 2 */
volatile SPIBRSTR _SPIBR;                                  /* SPI Baud Rate Register */
volatile SPICR1STR _SPICR1;                                /* SPI Control Register */
volatile SPICR2STR _SPICR2;                                /* SPI Control Register 2 */
volatile SPIDRSTR _SPIDR;                                  /* SPI Data Register */
volatile SPISRSTR _SPISR;                                  /* SPI Status Register */
volatile SWRSTSTR _SWRST;                                  /* Software Reset */
volatile SYNRSTR _SYNR;                                    /* CRG Synthesizer Register */
volatile TCTL1STR _TCTL1;                                  /* Timer Control Registers 1 */
volatile TCTL3STR _TCTL3;                                  /* Timer Control Register 3 */
volatile TFLG1STR _TFLG1;                                  /* Main Timer Interrupt Flag 1 */
volatile TFLG2STR _TFLG2;                                  /* Main Timer Interrupt Flag 2 */
volatile TIESTR _TIE;                                      /* Timer Interrupt Enable Register */
volatile TIOSSTR _TIOS;                                    /* Timer Input Capture/Output Compare Select */
volatile TSCR1STR _TSCR1;                                  /* Timer System Control Register1 */
volatile TSCR2STR _TSCR2;                                  /* Timer System Control Register 2 */
volatile TTOVSTR _TTOV;                                    /* Timer Toggle On Overflow Register */
volatile TXCTSSTR _TXCTS;                                  /* Transmit Control and Status */
volatile WOMLSTR _WOML;                                    /* Port L Wired-Or Mode Register */
volatile WOMSSTR _WOMS;                                    /* Port S Wired-Or Mode Register */
volatile ATDCTL23STR _ATDCTL23;                            /* ATD Control Register 23 */
volatile ATDCTL45STR _ATDCTL45;                            /* ATD Control Register 45 */
volatile ATDDIENSTR _ATDDIEN;                              /* ATD Input Enable Register */
volatile ATDDR0STR _ATDDR0;                                /* ATD Conversion Result Register 0 */
volatile ATDDR1STR _ATDDR1;                                /* ATD Conversion Result Register 1 */
volatile ATDDR2STR _ATDDR2;                                /* ATD Conversion Result Register 2 */
volatile ATDDR3STR _ATDDR3;                                /* ATD Conversion Result Register 3 */
volatile ATDDR4STR _ATDDR4;                                /* ATD Conversion Result Register 4 */
volatile ATDDR5STR _ATDDR5;                                /* ATD Conversion Result Register 5 */
volatile ATDDR6STR _ATDDR6;                                /* ATD Conversion Result Register 6 */
volatile ATDDR7STR _ATDDR7;                                /* ATD Conversion Result Register 7 */
volatile BUFCFGSTR _BUFCFG;                                /* FIFO Buffer Configuration */
volatile DBGCASTR _DBGCA;                                  /* Debug Comparator A Register */
volatile DBGCBSTR _DBGCB;                                  /* Debug Comparator B Register */
volatile DBGCCSTR _DBGCC;                                  /* Debug Comparator C Register */
volatile DBGTBSTR _DBGTB;                                  /* Debug Trace Buffer Register */
volatile DDRABSTR _DDRAB;                                  /* Port AB Data Direction Register */
volatile EMAC_MISCSTR _EMAC_MISC;                          /* MAC Address Register 3 */
volatile ETYPESTR _ETYPE;                                  /* Programmable Ethertype */
volatile IEVENTSTR _IEVENT;                                /* Interrupt Event */
volatile IMASKSTR _IMASK;                                  /* Interrupt Mask */
volatile MACAD0STR _MACAD0;                                /* MAC Address Register 0 */
volatile MACAD1STR _MACAD1;                                /* MAC Address Register 1 */
volatile MACAD2STR _MACAD2;                                /* MAC Address Register 2 */
volatile MCHASH0STR _MCHASH0;                              /* Multicast Hash Table Register 0 */
volatile MCHASH1STR _MCHASH1;                              /* Multicast Hash Table Register 1 */
volatile MCHASH2STR _MCHASH2;                              /* Multicast Hash Table Register 2 */
volatile MCHASH3STR _MCHASH3;                              /* Multicast Hash Table Register 3 */
volatile MRDATASTR _MRDATA;                                /* MII Read Data */
volatile MWDATASTR _MWDATA;                                /* MII Write Data */
volatile PACNTSTR _PACNT;                                  /* TIM Pulse Accumulators Count Register */
volatile PORTABSTR _PORTAB;                                /* Port AB Register */
volatile PTIMESTR _PTIME;                                  /* PAUSE Timer Value and Counter */
volatile RXAEFPSTR _RXAEFP;                                /* Receive A End of Frame Pointer */
volatile RXBEFPSTR _RXBEFP;                                /* Receive B End of Frame Pointer */
volatile SCI0BDSTR _SCI0BD;                                /* SCI 0 Baud Rate Register */
volatile SCI1BDSTR _SCI1BD;                                /* SCI 1 Baud Rate Register */
volatile TC4STR _TC4;                                      /* Timer Input Capture/Output Compare Register 4 */
volatile TC5STR _TC5;                                      /* Timer Input Capture/Output Compare Register 5 */
volatile TC6STR _TC6;                                      /* Timer Input Capture/Output Compare Register 6 */
volatile TC7STR _TC7;                                      /* Timer Input Capture/Output Compare Register 7 */
volatile TCNTSTR _TCNT;                                    /* Timer Count Register */
volatile TXEFPSTR _TXEFP;                                  /* Transmit End of Frame Pointer */
/*
** ###################################################################
**
**     This file was created by UNIS Processor Expert 03.44 for 
**     the Motorola HCS12 series of microcontrollers.
**          !!! DEVELOPER VERSION FOR INTERNAL USAGE ONLY !!!
**
** ###################################################################
*/